AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 3

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO Ordering Information
Note:
AGL1000
Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
Part Number
IGLOO Devices
IGLOO Devices with Cortex-M1
M1AGL1000 =
M1AGL250 =
M1AGL600 =
AGL1000 =
AGL015 =
AGL030 =
AGL060 =
AGL125 =
AGL250 =
AGL400 =
AGL600 =
V2
Supply Voltage
_
15,000 System Gates
30,000 System Gates
60,000 System Gates
125,000 System Gates
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
250,000 System Gates
600,000 System Gates
1,000,000 System Gates
2 = 1.2 V to 1.5 V
5 = 1.5 V only
FG
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
UC = Micro Chip Scale Package (0.4 mm pitch)
CS = Chip Scale Package (0.4 mm and 0.5 mm pitches)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
G
Lead-Free Packaging
Blank = Standard Packaging
144
G= RoHS-Compliant Packaging (some packages also halogen-free)
R ev i si o n 1 8
Package Lead Count
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
IGLOO Low Power Flash FPGAs
III