AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet

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AGL125V2-CSG196

Manufacturer Part Number
AGL125V2-CSG196
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGL125V2-CSG196

Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
CSP-196
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
November 2009
© 2010 Actel Corporation
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
High Capacity
Reprogrammable Flash Technology
In-System Programming (ISP) and Security
High-Performance Routing Hierarchy
Advanced I/O
IGLOO Devices
ARM-Enabled IGLOO Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. AES is not available for ARM-enabled IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
4. The M1AGL250 device does not support this package.
5. Device/package support TBD
6. The
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low Power Active FPGA Operation
• Flash*Freeze
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Segmented, Hierarchical Routing and Clock Structure
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
† AGL015 and AGL030 devices do not support this feature.
UC/CS
QFN
VQFP
FBGA
Consumption while Maintaining FPGA Content
Performance
Standard (AES) Decryption (except ARM
devices) via JTAG (IEEE 1532–compliant)
IGLOOe
®
datasheet and
to Secure FPGA Contents
3
1
Technology
2
IGLOOe FPGA Fabric User’s Guide
AGL015
QN68
15 k
128
384
1 k
49
Enables
5
6
2
QN48, QN68,
AGL030
QN132
VQ100
UC81
CS81
30 k
256
768
®
1 k
Ultra-Low
81
5
6
2
-enabled IGLOO
AGL060 AGL125
FG144
QN132
CS121
VQ100
1,536
60 k
512
Yes
1 k
10
18
18
96
4
1
2
Power
5
provide information on higher densities and additional features.
®
QN132
CS196
VQ100
FG144
125 k
1,024
3,072
Yes
133
1 k
16
36
18
8
1
2
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
ARM Processor Support in IGLOO FPGAs
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
• Wide Range Power Supply Voltage Support per JESD8-B,
• Wide Range Power Supply Voltage Support per JESD8-12,
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
• True Dual-Port SRAM (except ×18)
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
‡ Supported only by AGL015 and AGL030 devices.
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X
and LVCMOS 2.5 V / 5.0 V Input
LVDS (AGL250 and above)
Allowing I/Os to Operate from 2.7 V to 3.6 V
Allowing I/Os to Operate from 1.14 V to 1.575 V
and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
with or without Debug
M1AGL250
QN132
AGL250
CS196
VQ100
FG144
2,048
250 k
6,144
Yes
143
1 k
24
36
18
1
4
8
4,5
,4
FG144, FG256,
I/O
AGL400
CS196
FG484
400 k
9,216
194
Yes
1 k
32
54
12
18
1
4
Standards:
FG144, FG256,
M1AGL600
and Drive Strength
AGL600
CS281
FG484
13,824
600 k
108
Yes
235
1 k
36
24
18
1
4
LVTTL,
Revision 18
FG144, FG256,
M1AGL1000
AGL1000
24,576
CS281
FG484
1 M
144
Yes
300
LVCMOS
1 k
53
32
18
1
4
RAM
®
I
,

Related parts for AGL125V2-CSG196

AGL125V2-CSG196 Summary of contents

Page 1

... IGLOOe FPGA Fabric User’s Guide † AGL015 and AGL030 devices do not support this feature. November 2009 © 2010 Actel Corporation • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages— Banks per Chip • Single-Ended 3 ...

Page 2

IGLOO Low Power Flash FPGAs 1 I/Os Per Package IGLOO Devices AGL015 AGL030 ARM-Enabled IGLOO Devices Package QN48 – 34 QN68 49 49 UC81 – 66 CS81 – 66 CS121 – – VQ100 – 77 QN132 – 81 CS196 – ...

Page 3

IGLOO Ordering Information _ AGL1000 V2 FG Package Type Supply Voltage 1.5 V only Part Number IGLOO Devices AGL015 = 15,000 System Gates AGL030 = 30,000 System Gates AGL060 = 60,000 ...

Page 4

... AGL1000 References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. AGL015 and AGL030 The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features. ...

Page 5

... QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 IGLOO Low Power Flash FPGAs ...

Page 6

...

Page 7

... Cortex available for free from Actel for use in M1 IGLOO FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support AES decryption. Flash*Freeze Technology The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode ...

Page 8

... Live at Power-Up The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs ...

Page 9

... The versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...

Page 10

IGLOO Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface. ISP AES User Nonvolatile Decryption* FlashRom Note: *Not supported by AGL015 and AGL030 devices ...

Page 11

... VersaTile configurations. LUT-3 Equivalent D-Flip-Flop with Clear or Set X1 Data X2 LUT-3 CLK Y X3 CLR Figure 1-4 • VersaTile Configurations IGLOO Low Power Flash FPGAs Actel IGLOO FPGA Flash*Freeze Pin Enable D-Flip-Flop with Clear or Set Data Y D-FF CLK Enable CLR Figure 1-3 for an PLUS® ...

Page 12

... IGLOO Device Family Overview User Nonvolatile FlashROM Actel IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • ...

Page 13

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from ...

Page 14

... Wide Range I/O Support Actel IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1. 1.575 V. ...

Page 15

IGLOO DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...

Page 16

... All parameters representing voltages are measured with respect to GND unless otherwise specified. 5. VPUMP can be left floating during operation (not programming mode ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. ...

Page 17

Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or VCCI as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at junction temperature at 85°C. 2. ...

Page 18

... IGLOO DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± ...

Page 19

... Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. ...

Page 20

IGLOO DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is θ θ . The thermal characteristics for θ ja temperature is 110°C. allowed for the AGL1000-FG484 package at commercial temperature and in still air. Max. junction ...

Page 21

... Quiescent supply current (I (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature Table 2-8 • ...

Page 22

IGLOO DC and Switching Characteristics Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode* Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units VCCI/ VJTAG = 1.2 V 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = ...

Page 23

Table 2-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units 2 I Current CCA Typical (25° Current ...

Page 24

IGLOO DC and Switching Characteristics Power per I/O Pin Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3 3.3V ...

Page 25

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3 3.3V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS ...

Page 26

IGLOO DC and Switching Characteristics Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 4 3.3V LVCMOS Wide Range ...

Page 27

... RAM block during a write operation PAC13 Dynamic PLL contribution * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero Device Specific Dynamic Power (µW/MHz) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 14.48 12.77 12 ...

Page 28

... I/O input pin static power (standard-dependent) PDC7 I/O output pin static power (standard-dependent) * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero 2- 14 Device-Specific Static Power (mW) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 in ...

Page 29

... RAM block during a write operation PAC13 Dynamic PLL contribution * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE. Device Specific Dynamic Power (µW/MHz) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 9 ...

Page 30

... For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero 2- 16 Device Specific Static Power (mW) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 See Table 2-11 on page ...

Page 31

... Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • ...

Page 32

IGLOO DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in 1 page ...

Page 33

Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...

Page 34

IGLOO DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.43 ns ICLKQ t = 0.47 ns ISUD Input LVTTL Clock ...

Page 35

PY PAD t = MAX MAX(t DIN V trip PAD 50% Y GND t PY (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example) t DIN CLK I/O Interface ...

Page 36

IGLOO DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT t ...

Page 37

EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip VOL D 50 EOUT (R) VCC 50% EOUT t ZLS PAD Vtrip VOL Figure ...

Page 38

IGLOO DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ...

Page 39

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard Plus I/O Banks Equivalent Software Default Drive I/O Drive Strength Slew 2 Standard Strength Option Rate ...

Page 40

IGLOO DC and Switching Characteristics Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks Equivalen t Software Default Drive I/O Drive Strength 2 ...

Page 41

Table 2-27 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V ...

Page 42

IGLOO DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-28 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V VCMOS Wide Range 2.5 V LVCMOS 1.8 ...

Page 43

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Advanced I/O Banks 3 High 5 LVTTL / 3.3 V LVCMOS 3.3 V 100 µA 12 High ...

Page 44

IGLOO DC and Switching Characteristics Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Standard Plus I/O Banks 3 High LVTTL / 3.3 V LVCMOS 3.3 ...

Page 45

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Standard I/O Banks 3 High LVTTL / 3.3 V LVCMOS 3.3 V 100 µA 8 High LVCMOS ...

Page 46

IGLOO DC and Switching Characteristics Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Advanced I/O Banks 3 High LVTTL / 3.3 V LVCMOS 3.3 ...

Page 47

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Standard Plus I/O Banks 3 High 5 LVTTL / 3.3 V LVCMOS 3.3 V 100 µA 12 ...

Page 48

IGLOO DC and Switching Characteristics Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: T standard) Applicable to Standard I/O Banks 3 High LVTTL / 3.3 V LVCMOS 3.3 V ...

Page 49

... TBD 100 μA TBD Per PCI/PCI-X 25 specification IBIS models located O H spec IGLOO Low Power Flash FPGAs Min. Max. Units PULL-UP 3 (Ω) 300 300 150 150 TBD 200 200 100 100 50 40 224 112 TBD TBD 75 on the Actel website ...

Page 50

... TBD 100 μA TBD Per PCI/PCI-X specification IBIS models located OLspec O H spec sio PULL- (Ω) 300 300 50 150 50 150 TBD 200 200 50 100 50 100 25 50 225 112 224 112 TBD TBD the Actel website at ...

Page 51

... PULL-UP) (Ω) Max 110 K 110 (WEAK PULL-UP-MIN IGLOO Low Power Flash FPGAs R PULL-UP 3 (Ω) 300 300 150 150 TBD 200 200 100 100 225 112 224 TBD TBD on the Actel website (WEAK PULL-DOWN) (Ω) Min. Max 110 140 150 150 ...

Page 52

IGLOO DC and Switching Characteristics Table 2-41 • I/O Short Currents I Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V ...

Page 53

Table 2-42 • I/O Short Currents I OSH Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V ...

Page 54

... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals ...

Page 55

Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros ...

Page 56

IGLOO DC and Switching Characteristics Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.8 4 ...

Page 57

Timing Characteristics Applies to 1 Core Voltage Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed ...

Page 58

IGLOO DC and Switching Characteristics Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade 4 mA Std. ...

Page 59

Applies to 1 Core Voltage Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade t ...

Page 60

IGLOO DC and Switching Characteristics Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade ...

Page 61

V LVCMOS Wide Range Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Advanced I/O Banks 3.3 V LVCMOS Wide Range VIL Equivalent Software Default Drive Drive Strength Min. ...

Page 62

IGLOO DC and Switching Characteristics Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Drive Strength Min. ...

Page 63

Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard I/O Banks 3.3 V LVCMOS Wide Range VIL Equivalent Software Default Drive Drive Strength Min. Max. 1 Strength Option V ...

Page 64

IGLOO DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-66 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced Banks Equivalent ...

Page 65

Table 2-68 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 ...

Page 66

IGLOO DC and Switching Characteristics Table 2-70 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Banks Equivalent Software Default Drive Drive Strength Speed 1 Strength Option ...

Page 67

Applies to 1 Core Voltage Table 2-72 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced Banks Equivalent Software Default Drive Drive Strength Speed 1 ...

Page 68

IGLOO DC and Switching Characteristics Table 2-74 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Equivalent Software Default Drive Drive Strength Speed 1 Strength ...

Page 69

Table 2-76 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Banks Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µA ...

Page 70

IGLOO DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...

Page 71

Table 2-80 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS VIL VIH Drive Min. Max. Min. Strength –0.3 0.7 1 –0.3 0.7 1.7 6 ...

Page 72

IGLOO DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-82 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength ...

Page 73

Table 2-85 • 2.5 V LVCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade t DOUT 4 mA Std. 0. Std. 0. ...

Page 74

IGLOO DC and Switching Characteristics Applies to 1.2 V Core Voltage Table 2-88 • 2.5 V LCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade t ...

Page 75

Table 2-91 • 2.5 V LCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade t DOUT 4 mA Std. 1. Std. 1. ...

Page 76

IGLOO DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. ...

Page 77

Table 2-96 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMO S VIL Drive Min. Max. Min. Strength –0.3 0.35 * VCCI 0.65 * VCCI 4 mA ...

Page 78

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-98 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade ...

Page 79

Table 2-101 • 1.8 V LVCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade t DOUT 2 mA Std. 0. Std. 0. ...

Page 80

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-104 • 1.8 V LCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade t 2 ...

Page 81

Table 2-107 • 1.8 V LCMOS High Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus Banks Drive Strength Speed Grade t DOUT 2 mA Std. 1. Std. 1. ...

Page 82

IGLOO DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...

Page 83

Table 2-112 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS VIL Drive Min. Max. Min. Strength –0.3 0.35 * VCCI 0.65 * VCCI Notes ...

Page 84

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-114 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade ...

Page 85

Table 2-118 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Banks Drive Strength Speed Grade 2 mA Std. Note: For specific junction temperature and voltage supply levels, refer ...

Page 86

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-120 • 1.5 V LCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade t 2 ...

Page 87

Table 2-124 • 1.5 V LCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Banks Drive Strength Speed Grade 2 mA Std. Note: For specific junction temperature and voltage supply levels, refer ...

Page 88

IGLOO DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Furthermore, all ...

Page 89

Test Point Datapath 5 pF Figure 2-11 • AC Loading Table 2-129 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High ( Measuring point = Vtrip. See Table 2-28 on page 2- ...

Page 90

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-130 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Strength Speed Grade Std. Note: For specific junction ...

Page 91

V LCMOS Wide Range Table 2-136 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Advanced I/O Banks 1.2 V LVCMOS Wide Range VIL Equivalent Software Default Drive Drive Strength Min. ...

Page 92

IGLOO DC and Switching Characteristics Table 2-138 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Standard I/O Banks 1.2 V LVCMOS Wide Range VIL Equivalent Software Default Drive Drive Strength Min. ...

Page 93

... Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described VCCI for GND for t ...

Page 94

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-142 • 3.3 V PCI/PCI-X Commercial-Case Conditions: T Applicable to Advanced I/O Banks Speed Grade t t DOUT DP Std. 0.97 2.32 Note: For specific junction temperature ...

Page 95

... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...

Page 96

IGLOO DC and Switching Characteristics Table 2-146 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI Supply Voltage VOL Output Low Voltage VOH Output High Voltage 4 I Output Lower Current Output High Current ...

Page 97

... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...

Page 98

IGLOO DC and Switching Characteristics Table 2-150 • Minimum and Maximum DC Input and Output Levels DC Parameter Description VCCI Supply Voltage VOL Output Low Voltage VOH Output High Voltage VIL, VIH Input Low, Input High Voltages V Differential Output ...

Page 99

I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-16 • Timing ...

Page 100

IGLOO DC and Switching Characteristics Table 2-154 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 101

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-17 • Timing Model of ...

Page 102

IGLOO DC and Switching Characteristics Table 2-155 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 103

Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-18 • Input Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-156 • Input Data Register Propagation ...

Page 104

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-157 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data Register ISUD ...

Page 105

Timing Characteristics 1 Core Voltage Table 2-158 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold ...

Page 106

IGLOO DC and Switching Characteristics Output Enable Register 50% CLK 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT Figure 2-20 • Output Enable Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-160 • ...

Page 107

V DC Core Voltage Table 2-161 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD t Data Hold Time for ...

Page 108

IGLOO DC and Switching Characteristics DDR Module Specifications Input DDR Module INBUF Data CLK CLKBUF CLR INBUF Figure 2-21 • Input DDR Timing Model Table 2-162 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...

Page 109

CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-22 • Input DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-163 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out ...

Page 110

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-164 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input ...

Page 111

Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-23 • Output DDR Timing Model Table 2-165 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t Clear Removal DDROREMCLR t Clear ...

Page 112

IGLOO DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-24 • Output DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-166 • Output DDR Propagation ...

Page 113

V DC Core Voltage Table 2-167 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDROSUD1 t Data_R Data Setup for Output DDR DDROSUD2 ...

Page 114

IGLOO DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer ...

Page 115

Fanout = 4 Length = 1 VersaTile Net Length = 1 VersaTile Net Length = 1 VersaTile Net Length = 1 VersaTile 50 50% OUT GND t PD (RR) VCC OUT (RF) Figure 2-26 • Timing Model ...

Page 116

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-168 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and ...

Page 117

VersaTile Specifications as a Sequential Module The IGLOO library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a ...

Page 118

IGLOO DC and Switching Characteristics 50% CLK 50% Data EN 50 PRE SUE CLR Out Figure 2-28 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-170 • Register Delays Commercial-Case Conditions: T ...

Page 119

V DC Core Voltage Table 2-171 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for the Core Register HD t ...

Page 120

IGLOO DC and Switching Characteristics Global Resource Characteristics AGL250 Clock Tree Topology Clock delays are device-specific. global tree presented in is used to drive all D-flip-flops in the device. CCC Figure 2-29 • Example of Global Tree Use in an ...

Page 121

Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and ...

Page 122

IGLOO DC and Switching Characteristics Table 2-174 • AGL060 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH ...

Page 123

Table 2-176 • AGL250 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width Low ...

Page 124

IGLOO DC and Switching Characteristics Table 2-178 • AGL600 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH ...

Page 125

V DC Core Voltage Table 2-180 • AGL015 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH ...

Page 126

IGLOO DC and Switching Characteristics Table 2-182 • AGL060 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH ...

Page 127

Table 2-184 • AGL250 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width Low ...

Page 128

IGLOO DC and Switching Characteristics Table 2-186 • AGL600 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH ...

Page 129

Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-188 • IGLOO CCC/PLL Specification For IGLOO Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay ...

Page 130

IGLOO DC and Switching Characteristics Table 2-189 • IGLOO CCC/PLL Specification For IGLOO V2 Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks ...

Page 131

Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-30 • Peak-to-Peak Jitter Definition IGLOO Low Power Flash FPGAs T T period_max period_min = T – T peak-to-peak period_max period_min ...

Page 132

IGLOO DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-31 • RAM Models RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...

Page 133

Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-32 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...

Page 134

IGLOO DC and Switching Characteristics CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-34 • RAM Write, Output Retained (WMODE = 0) CLK ADD t BKS ...

Page 135

CLK1 ADD1 DI1 CCKH CLK2 WEN_B1 WEN_B2 A ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-36 • Write Access after Write onto Same Address ...

Page 136

CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-37 • Read Access after Write onto Same Address WRO t ...

Page 137

CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-38 • Write Access after Read onto Same Address t CKH CLK ...

Page 138

IGLOO DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-190 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold ...

Page 139

Table 2-191 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...

Page 140

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-192 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH ...

Page 141

Table 2-193 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...

Page 142

IGLOO DC and Switching Characteristics FIFO Figure 2-40 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...

Page 143

Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-41 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-42 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...

Page 144

IGLOO DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-43 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...

Page 145

Timing Characteristics 1 Core Voltage Table 2-194 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...

Page 146

IGLOO DC and Switching Characteristics 1 Core Voltage Table 2-195 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time ...

Page 147

Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-46 • Timing Diagram Timing Characteristics 1 Core Voltage Table 2-196 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: T Parameter t Address Setup Time ...

Page 148

IGLOO DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...

Page 149

... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...

Page 150

IGLOO DC and Switching Characteristics isio ...

Page 151

... Package Pin Assignments 81-Pin µCSP 9 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner IGLOO Low Power Flash FPGAs ...

Page 152

Package Pin Assignments 81-Pin µCSP Pin Number AGL030 Function A1 IO00RSB0 A2 IO02RSB0 A3 IO06RSB0 A4 IO11RSB0 A5 IO16RSB0 A6 IO19RSB0 A7 IO22RSB0 A8 IO24RSB0 A9 IO26RSB0 B1 IO81RSB1 B2 IO04RSB0 B3 IO10RSB0 B4 IO13RSB0 B5 IO15RSB0 B6 IO20RSB0 B7 ...

Page 153

... CSP 9 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner IGLOO Low Power Flash FPGAs ...

Page 154

Package Pin Assignments 81-Pin CSP Pin Number AGL030 Function A1 IO00RSB0 A2 IO02RSB0 A3 IO06RSB0 A4 IO11RSB0 A5 IO16RSB0 A6 IO19RSB0 A7 IO22RSB0 A8 IO24RSB0 A9 IO26RSB0 B1 IO81RSB1 B2 IO04RSB0 B3 IO10RSB0 B4 IO13RSB0 B5 IO15RSB0 B6 IO20RSB0 B7 ...

Page 155

... CSP 11 10 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx IGLOO Low Power Flash FPGAs ...

Page 156

Package Pin Assignments 121-Pin CSP Pin Number AGL060 Function A1 GNDQ A2 IO01RSB0 A3 GAA1/IO03RSB0 A4 GAC1/IO07RSB0 A5 IO15RSB0 A6 IO13RSB0 A7 IO17RSB0 A8 GBB1/IO22RSB0 A9 GBA1/IO24RSB0 A10 GNDQ A11 VMV0 B1 GAA2/IO95RSB1 B2 IO00RSB0 B3 GAA0/IO02RSB0 B4 GAC0/IO06RSB0 B5 ...

Page 157

CSP Pin Number AGL060 Function K10 VPUMP K11 GDB1/IO47RSB0 L1 VMV1 L2 GNDQ L3 IO65RSB1 L4 IO63RSB1 L5 IO61RSB1 L6 IO58RSB1 L7 IO57RSB1 L8 IO55RSB1 L9 GNDQ L10 GDA0/IO50RSB0 L11 VMV1 IGLOO Low Power Flash FPGAs ...

Page 158

... Package Pin Assignments 196-Pin CSP 14 13 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner isio ...

Page 159

CSP Pin Number AGL125 Function A1 GND A2 GAA0/IO00RSB0 A3 GAC0/IO04RSB0 A4 GAC1/IO05RSB0 A5 IO09RSB0 A6 IO15RSB0 A7 IO18RSB0 A8 IO22RSB0 A9 IO27RSB0 A10 GBC0/IO35RSB0 A11 GBB0/IO37RSB0 A12 GBB1/IO38RSB0 A13 GBA1/IO40RSB0 A14 GND B1 VCCIB1 B2 VMV0 B3 GAA1/IO01RSB0 ...

Page 160

Package Pin Assignments 196-Pin CSP Pin Number AGL125 Function H11 GCB0/IO54RSB0 H12 GCA1/IO55RSB0 H13 IO49RSB0 H14 GCA2/IO57RSB0 J1 GFC2/IO115RSB1 J2 IO110RSB1 J3 IO94RSB1 J4 IO93RSB1 J5 IO89RSB1 VCC J8 VCC J9 NC J10 IO60RSB0 J11 GCB2/IO58RSB0 J12 ...

Page 161

CSP Pin Number AGL250 Function A1 GND A2 GAA0/IO00RSB0 A3 GAC0/IO04RSB0 A4 GAC1/IO05RSB0 A5 IO10RSB0 A6 IO13RSB0 A7 IO17RSB0 A8 IO19RSB0 A9 IO23RSB0 A10 GBC0/IO35RSB0 A11 GBB0/IO37RSB0 A12 GBB1/IO38RSB0 A13 GBA1/IO40RSB0 A14 GND B1 VCCIB3 B2 VMV0 B3 GAA1/IO01RSB0 ...

Page 162

Package Pin Assignments 196-Pin CSP Pin Number AGL250 Function H11 GCB0/IO49NDB1 H12 GCA1/IO50PDB1 H13 IO51NDB1 H14 GCA2/IO51PDB1 J1 GFC2/IO105PDB3 J2 IO104PPB3 J3 IO106NPB3 J4 IO103PDB3 J5 IO103NDB3 J6 IO80RSB2 J7 VCC J8 VCC J9 IO64RSB2 J10 IO56PDB1 J11 GCB2/IO52PDB1 J12 ...

Page 163

CSP Pin Number AGL400 Function A1 GND A2 GAA0/IO00RSB0 A3 GAC0/IO04RSB0 A4 GAC1/IO05RSB0 A5 IO14RSB0 A6 IO18RSB0 A7 IO26RSB0 A8 IO29RSB0 A9 IO36RSB0 A10 GBC0/IO54RSB0 A11 GBB0/IO56RSB0 A12 GBB1/IO57RSB0 A13 GBA1/IO59RSB0 A14 GND B1 VCCIB3 B2 VMV0 B2 VMV0 ...

Page 164

Package Pin Assignments 196-Pin CSP Pin Number AGL400 Function H10 GCC1/IO67PDB1 H11 GCB0/IO68NDB1 H12 GCA1/IO69PDB1 H13 IO70NDB1 H14 GCA2/IO70PDB1 J1 GFC2/IO142PDB3 J2 IO141PPB3 J3 IO143NPB3 J4 IO140PDB3 J5 IO140NDB3 J6 IO109RSB2 J7 VCC J8 VCC J9 IO84RSB2 J10 IO75PDB1 J11 ...

Page 165

... CSP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx IGLOO Low Power Flash FPGAs ...

Page 166

Package Pin Assignments 281-Pin CSP Pin Number AGL600 Function A1 GND A2 GAB0/IO02RSB0 A3 GAC1/IO05RSB0 A4 IO07RSB0 A5 IO10RSB0 A6 IO14RSB0 A7 IO18RSB0 A8 IO21RSB0 A9 IO22RSB0 A10 VCCIB0 A11 IO33RSB0 A12 IO40RSB0 A13 IO37RSB0 A14 IO48RSB0 A15 IO51RSB0 A16 ...

Page 167

CSP Pin Number AGL600 Function H8 VCC H9 VCCIB0 H10 VCC H11 VCCIB0 H12 VCC H13 VCCIB1 H15 IO68NPB1 H16 GCB0/IO70NPB1 H18 GCA1/IO71PPB1 H19 GCA2/IO72PPB1 J1 VCOMPLF J2 GFA0/IO162NDB3 J4 VCCPLF J5 GFC0/IO164NPB3 J7 GFA2/IO161PDB3 J8 VCCIB3 J9 GND ...

Page 168

Package Pin Assignments 281-Pin CSP Pin Number AGL600 Function R15 IO94RSB2 R16 GDA1/IO88PPB1 R18 GDB0/IO87NPB1 R19 GDC0/IO86NPB1 T1 IO148PPB3 T2 GEC0/IO146NPB3 T4 GEB0/IO145NPB3 T5 IO132RSB2 T6 IO136RSB2 T7 IO130RSB2 T8 IO126RSB2 T9 IO120RSB2 T10 GND T11 IO113RSB2 T12 IO104RSB2 T13 ...

Page 169

CSP Pin Number AGL1000 Function A1 GND A2 GAB0/IO02RSB0 A3 GAC1/IO05RSB0 A4 IO13RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO20RSB0 A8 IO24RSB0 A9 IO29RSB0 A10 VCCIB0 A11 IO39RSB0 A12 IO45RSB0 A13 IO48RSB0 A14 IO58RSB0 A15 IO61RSB0 A16 IO62RSB0 A17 GBC1/IO73RSB0 ...

Page 170

Package Pin Assignments 281-Pin CSP Pin Number AGL1000 Function H8 VCC H9 VCCIB0 H10 VCC H11 VCCIB0 H12 VCC H13 VCCIB1 H15 IO90NPB1 H16 GCB0/IO92NPB1 H18 GCA1/IO93PPB1 H19 GCA2/IO94PPB1 J1 VCOMPLF J2 GFA0/IO207NDB3 J4 VCCPLF J5 GFC0/IO209NPB3 J7 GFA2/IO206PDB3 J8 ...

Page 171

CSP Pin Number AGL1000 Function R15 IO122RSB2 R16 GDA1/IO113PPB1 R18 GDB0/IO112NPB1 R19 GDC0/IO111NPB1 T1 IO197PPB3 T2 GEC0/IO190NPB3 T4 GEB0/IO189NPB3 T5 IO181RSB2 T6 IO172RSB2 T7 IO171RSB2 T8 IO156RSB2 T9 IO159RSB2 T10 GND T11 IO139RSB2 T12 IO138RSB2 T13 IO129RSB2 T14 IO123RSB2 ...

Page 172

... Package Pin Assignments 48-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Pin sio ...

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QFP Pin Number AGL030 Function 1 IO82RSB1 2 GEC0/IO73RSB1 3 GEA0/IO72RSB1 4 GEB0/IO71RSB1 5 GND 6 VCCIB1 7 IO68RSB1 8 IO67RSB1 9 IO66RSB1 10 IO65RSB1 11 IO64RSB1 12 IO62RSB1 13 IO61RSB1 14 FF/IO60RSB1 15 IO57RSB1 16 IO55RSB1 17 IO53RSB1 ...

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... Package Pin Assignments 68-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Pin A1 Mark sio ...

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QFN Pin Number AGL015 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 IO63RSB1 17 IO62RSB1 ...

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Package Pin Assignments 68-Pin QFN Pin Number AGL030 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 ...

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... B23 A25 D3 A24 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A48 B44 C31 C40 C20 C11 B12 B22 ...

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Package Pin Assignments 132-Pin QFN Pin Number AGL030 Function A1 IO80RSB1 A2 IO77RSB1 IO76RSB1 A5 GEC0/IO73RSB1 GEB0/IO71RSB1 A8 IO69RSB1 A9 NC A10 VCC A11 IO67RSB1 A12 IO64RSB1 A13 IO59RSB1 A14 IO56RSB1 A15 NC A16 ...

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QFN Pin Number AGL030 Function C17 IO47RSB1 C18 NC C19 TCK C20 NC C21 VPUMP C22 VJTAG C23 NC C24 NC C25 NC C26 GDB0/IO34RSB0 C27 NC C28 VCCIB0 C29 IO28RSB0 C30 IO25RSB0 C31 IO24RSB0 C32 IO21RSB0 C33 NC ...

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Package Pin Assignments 132-Pin QFN Pin Number AGL060 Function A1 GAB2/IO00RSB1 A2 IO93RSB1 A3 VCCIB1 A4 GFC1/IO89RSB1 A5 GFB0/IO86RSB1 A6 VCCPLF A7 GFA1/IO84RSB1 A8 GFC2/IO81RSB1 A9 IO78RSB1 A10 VCC A11 GEB1/IO75RSB1 A12 GEA0/IO72RSB1 A13 GEC2/IO69RSB1 A14 IO65RSB1 A15 VCC A16 ...

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QFN Pin Number AGL060 Function C17 IO57RSB1 C18 NC C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO42RSB0 C27 GCC0/IO39RSB0 C28 VCCIB0 C29 IO29RSB0 C30 GNDQ C31 GBA1/IO27RSB0 C32 GBB0/IO24RSB0 C33 VCC ...

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Package Pin Assignments 132-Pin QFN Pin Number AGL125 Function A1 GAB2/IO69RSB1 A2 IO130RSB1 A3 VCCIB1 A4 GFC1/IO126RSB1 A5 GFB0/IO123RSB1 A6 VCCPLF A7 GFA1/IO121RSB1 A8 GFC2/IO118RSB1 A9 IO115RSB1 A10 VCC A11 GEB1/IO110RSB1 A12 GEA0/IO107RSB1 A13 GEC2/IO104RSB1 A14 IO100RSB1 A15 VCC A16 ...

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QFN Pin Number AGL125 Function C16 IO89RSB1 C17 IO83RSB1 C18 VCCIB1 C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO55RSB0 C27 GCC0/IO52RSB0 C28 VCCIB0 C29 IO42RSB0 C30 GNDQ C31 GBA1/IO40RSB0 C32 GBB0/IO37RSB0 ...

Page 184

... Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx sio ...

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VQFP Pin Number AGL030 Function 1 GND 2 IO82RSB1 3 IO81RSB1 4 IO80RSB1 5 IO79RSB1 6 IO78RSB1 7 IO77RSB1 8 IO76RSB1 9 GND 10 IO75RSB1 11 IO74RSB1 12 GEC0/IO73RSB1 13 GEA0/IO72RSB1 14 GEB0/IO71RSB1 15 IO70RSB1 16 IO69RSB1 17 VCC ...

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Package Pin Assignments 100-Pin VQFP Pin Number AGL060 Function 1 GND 2 GAA2/IO51RSB1 3 IO52RSB1 4 GAB2/IO53RSB1 5 IO95RSB1 6 GAC2/IO94RSB1 7 IO93RSB1 8 IO92RSB1 9 GND 10 GFB1/IO87RSB1 11 GFB0/IO86RSB1 12 VCOMPLF 13 GFA0/IO85RSB1 14 VCCPLF 15 GFA1/IO84RSB1 16 ...

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VQFP Pin Number AGL125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 7 IO130RSB1 8 IO129RSB1 9 GND 10 GFB1/IO124RSB1 11 GFB0/IO123RSB1 12 VCOMPLF 13 GFA0/IO122RSB1 14 VCCPLF 15 GFA1/IO121RSB1 16 GFA2/IO120RSB1 17 VCC ...

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Package Pin Assignments 100-Pin VQFP Pin Number AGL250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO112PSB3 9 GND 10 GFB1/IO109PDB3 11 GFB0/IO109NDB3 12 VCOMPLF 13 GFA0/IO108NPB3 14 VCCPLF 15 GFA1/IO108PPB3 16 ...

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... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner IGLOO Low Power Flash FPGAs ...

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Package Pin Assignments 144-Pin FBGA Pin Number AGL125 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO11RSB0 A6 GND A7 IO18RSB0 A8 VCC A9 IO25RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO69RSB1 B2 GND B3 GAA0/IO00RSB0 B4 ...

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FBGA Pin Number AGL125 Function K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 FF/GEB2/IO105RSB 1 L4 IO102RSB1 L5 ...

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Package Pin Assignments 144-Pin FBGA Pin Number AGL250 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

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FBGA Pin Number AGL250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 ...

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Package Pin Assignments 144-Pin FBGA Pin Number AGL400 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO30RSB0 A8 VCC A9 IO34RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO154UDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

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FBGA Pin Number AGL400 Function K1 GEB0/IO136NDB3 K2 GEA1/IO135PDB3 K3 GEA0/IO135NDB3 K4 GEA2/IO134RSB2 K5 IO127RSB2 K6 IO121RSB2 K7 GND K8 IO104RSB2 K9 GDC2/IO82RSB2 K10 GND K11 GDA0/IO79VDB1 K12 GDB0/IO78VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO133RS B2 L4 IO128RSB2 L5 ...

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Package Pin Assignments 144-Pin FBGA Pin Number AGL600 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 A8 VCC A9 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

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FBGA Pin Number AGL600 Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO142RSB 2 L4 IO136RSB2 L5 ...

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Package Pin Assignments 144-Pin FBGA Pin Number AGL1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

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FBGA Pin Number AGL1000 Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO186RSB 2 L4 IO172RSB2 L5 ...

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... Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner sio ...

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