AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 25

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Single-Ended
Notes:
1. PDC6 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO V2 devices only.
Single-Ended
Differential
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P
3. P
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V LVTTL / 3.3 V LVCMOS
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
DC7
AC10
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCCI.
Applicable to Standard I/O Banks
Applicable to Advanced I/O Banks
4
5
3
4
4
5
C
LOAD
10
10
5
5
5
5
5
5
5
–
–
VCCI (V)
(pF)
1.2
1.2
3.3
3.3
2.5
1.8
1.5
R ev i si o n 1 8
VCCI (V)
1.2
1.2
3.3
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
Static Power
PDC6 (mW)
Static Power
PDC7 (mW)
–
–
–
–
–
–
–
19.54
7.74
1
–
–
–
–
–
–
–
–
–
2
IGLOO Low Power Flash FPGAs
PAC9 (µW/MHz)
Dynamic Power
PAC10 (µW/MHz)
Dynamic Power
1
17.24
17.24
5.64
2.63
1.97
0.57
0.57
136.95
136.95
194.05
194.05
156.22
339.35
76.84
49.31
33.36
16.24
16.24
2
3
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