AGL125V2-CSG196 Actel, AGL125V2-CSG196 Datasheet - Page 100

• Manufacturer Part Number: AGL125V2-CSG196
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of AGL125V2-CSG196

• Processor Series: AGL125
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 125 K
• Package / Case: CSP-196
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO DC and Switching Characteristics
Table 2-154 • Parameter Definition and Measuring Nodes
2- 86
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OPRE2Q
OREMPRE
ORECPRE
OECLKQ
OESUD
OEHD
OESUE
OEHE
OEPRE2Q
OEREMPRE
OERECPRE
ICLKQ
ISUD
IHD
ISUE
IHE
IPRE2Q
IREMPRE
IRECPRE
*See
Figure 2-16 on page 2-85
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 8
Measuring Nodes
(from, to)*
H, DOUT
H, EOUT
L, DOUT
I, EOUT
G, H
G, H
K, H
K, H
C, A
C, A
D, E
D, A
F, H
L, H
L, H
J, H
A, E
B, A
B, A
D, A
F, H
J, H
I, H
I, H