FDME1034CZT Fairchild Semiconductor, FDME1034CZT Datasheet - Page 8

• Manufacturer Part Number: FDME1034CZT
• Description: MOSFET N/P-CH 20V 6-MICROFET
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDME1034CZT

• Fet Type: N and P-Channel
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 66 mOhm @ 3.4A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 3.8A, 2.6A
• Vgs(th) (max) @ Id: 1V @ 250µA
• Gate Charge (qg) @ Vgs: 4.2nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 300pF @ 10V
• Power - Max: 600mW
• Mounting Type: Surface Mount
• Package / Case: 6-MLP, 6-MicroFET™
• Configuration: Dual
• Transistor Polarity: N and P-Channel
• Resistance Drain-source Rds (on): 55 mOhms, 95 mOhms
• Drain-source Breakdown Voltage: 20 V, - 20 V
• Continuous Drain Current: 3.4 A, - 2.3 A
• Power Dissipation: 1.3 W
• Maximum Operating Temperature: + 150 C
• Forward Transconductance Gfs (max / Min): 9 S, 7 S
• Gate Charge Qg: 3 nC, 5.5 nC
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Module Configuration: Dual
• Continuous Drain Current Id: 3.8A
• Drain Source Voltage Vds: 20V
• On Resistance Rds(on): 0.055ohm
• Rds(on) Test Voltage Vgs: 4.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FDME1034CZT Rev.C1
©2010 Fairchild Semiconductor Corporation
Typical Characteristics (Q2 P-Channel)
0.01
4.5
3.0
1.5
0.0
0.1
10
Figure 19. Gate Charge Characteristics
1000
1
0.1
100
0
0.3
10
10
1
THIS AREA IS
LIMITED BY r
SINGLE PULSE
T
R
T
I
D
J
θ
A
-4
JA
Figure 21. Forward Bias Safe
= MAX RATED
= -2.3 A
= 25
= 195
-V
o
C
DS
o
C/W
, DRAIN to SOURCE VOLTAGE (V)
Operating Area
DS(on)
Q
g
2
, GATE CHARGE (nC)
1
10
V
-3
V
DD
DD
= -8 V
= -12 V
Fig 23. Single Pulse Maximum Power Dissipation
V
DD
4
= -10 V
10
10
-2
100 us
1 ms
10 ms
100 ms
1 s
10 s
DC
t, PULSE WIDTH (s)
60
6
10
-1
8
T
J
= 25°C unless otherwise noted
1000
1
10
10
10
10
10
10
10
10
10
Figure 22. Gate Leakage Current vs
100
10
-1
-2
-3
-4
-5
-6
-7
-8
-9
0.1
0
Figure 20. Capacitance vs Drain
V
f = 1 MHz
V
DS
GS
Gate to Source Voltage
= 0 V
= 0 V
-V
-V
to Source Voltage
3
DS
GS ,
10
, DRAIN TO SOURCE VOLTAGE (V)
GATE TO SOURCE VOLTAGE (V)
T
J
= 125
6
1
o
SINGLE PULSE
R
T
C
A
θ
JA
= 25
T
= 195
J
100
= 25
o
9
C
o
C/W
o
C
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C
C
C
10
iss
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1000
20
15