MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 54

• Manufacturer Part Number: MFRC53101T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53101T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2224-5; 935269691112; MFRC531; MFRC53101TD

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
10.5.2.4 CollPos register
Table 58.
[1]
Bit position of the first bit-collision detected on the RF interface.
Table 59.
Table 60.
Remark: A bit collision is not indicated in the CollPos register when using the
ISO/IEC 14443 B protocol standard.
Bit
5
4
3
2
1
0
Bit
Symbol
Access
Bit
7 to 0
Only valid for communication using ISO/IEC 14443 A.
Symbol
AccessErr
FIFOOvfl
CRCErr
FramingErr
ParityErr
CollErr
Symbol
CollPos[7:0] this register shows the bit position of the first detected collision in a
ErrorFlag register bit descriptions
CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
CollPos register bit descriptions
Value
1
0
1
1
0
1
0
1
0
1
0
7
Description
received frame.
Example:
Rev. 3.4 — 26 January 2010
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1
...
08h indicates a bit collision in the 8
Description
set when the access rights to the EEPROM are violated
set when an EEPROM related command starts
set when the microprocessor or MFRC531 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
set when RxCRCEn is set and the CRC fails
automatically set during the PrepareRx state in the receiver start
phase
set when the SOF is incorrect
automatically set during the PrepareRx state in the receiver start
phase
set when the parity check fails
automatically set during the PrepareRx state in the receiver start
phase
set when a bit-collision is detected
automatically set during the PrepareRx state in the receiver start
phase
6
056634
[1]
5
…continued
4
CollPos[7:0]
R
st
th
3
bit
bit
[1]
ISO/IEC 14443 reader IC
2
MFRC531
© NXP B.V. 2010. All rights reserved.
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