MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 28

• Manufacturer Part Number: MFRC53101T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53101T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2224-5; 935269691112; MFRC531; MFRC53101TD

NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
9.7.2 Reset phase
9.7.3 Initialization phase
9.7.4 Initializing the parallel interface type
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see
Remark: When the internal oscillator is used, time (t
become stable. This is because the internal oscillator is supplied by V
cycles will not be detected by the internal logic until V
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see
Remark: During the production test, the MFRC531 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC531’s start-up. See
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC531 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed:
•
•
•
•
the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC531 is ready to be
controlled
write 80h to the Page register to initialize the microprocessor interface
read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized
write 00h to the Page registers to activate linear addressing mode.
Rev. 3.4 — 26 January 2010
056634
Section 10.5 on page
Section 9.1.3 on page 8
Section 9.2.2 on page
osc
DDA
48).
) is required for the oscillator to
is stable.
for detailed information on the
13).
ISO/IEC 14443 reader IC
MFRC531
DDA
© NXP B.V. 2010. All rights reserved.
and any clock
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