MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 27

• Manufacturer Part Number: MFRC53101T/0FE,112
• Description: IC MIFARE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC53101T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2224-5; 935269691112; MFRC531; MFRC53101TD

NXP Semiconductors
MFRC531_34
Product data sheet
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9.6.3 Standby mode
9.6.4 Automatic receiver power-down
9.7.1 Hard power-down phase
9.7 StartUp phase
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
The events executed during the StartUp phase are shown in
The hard power-down phase is active during the following cases:
Remark: In case two, HIGH level on pin RSTPD, has to be at least 100 μs long (t
μs). Shorter phases will not necessarily result in the reset phase t
rising/falling edge on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger
input.
Fig 9.
•
•
a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when V
a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 μs (t
necessarily result in the reset phase (t
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
states
The StartUp procedure
DDD
or V
DDA
Hard power-
down phase
Rev. 3.4 — 26 January 2010
t
RSTPD
is below the digital reset threshold.
056634
StartUp phase
Reset phase
reset
t
reset
). The rising or falling edge slew rate on pin
PD
≥ 100 μs). Shorter phases will not
Figure
Initialising
ISO/IEC 14443 reader IC
phase
t
reset
init
9.
MFRC531
. The slew rate of
© NXP B.V. 2010. All rights reserved.
001aak613
ready
PD
27 of 116
≥ 100