MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 18
![IC MIFARE HS READER 32-SOIC](/photos/7/0/70098/568-32-soic_sot287-1_sml.jpg)
MFRC53101T/0FE,112
Manufacturer Part Number
MFRC53101T/0FE,112
Description
IC MIFARE HS READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Specifications of MFRC53101T/0FE,112
Rf Type
Read Only
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B, ISO15693
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2224-5
935269691112
MFRC531
MFRC53101TD
935269691112
MFRC531
MFRC53101TD
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MFRC53101T/0FE,112
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
9.3.2 Controlling the FIFO buffer
9.3.3 FIFO buffer status information
Table 17.
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
The microprocessor can get the following FIFO buffer status data:
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The MFRC531 can generate an interrupt signal when:
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by
HiAlert
LoAlert
Active
command
ReadE2
LoadKeyE2
LoadKey
Authent1
Authent2
LoadConfig
CalcCRC
•
•
•
•
•
•
the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
the FIFO buffer full warning: bit HiAlert
the FIFO buffer empty warning: bit LoAlert
the FIFO buffer overflow warning: bit FIFOOvfl.
bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
=
=
FIFO buffer access
(
FIFOLength
64 FIFOLength
–
FIFO buffer
μp Write
yes
yes
yes
yes
-
yes
yes
Rev. 3.4 — 26 January 2010
≤
WaterLevel
μp Read
yes
-
-
-
-
-
-
…continued
)
056634
≤
WaterLevel
Remark
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
Equation
Equation
1:
ISO/IEC 14443 reader IC
MFRC531
© NXP B.V. 2010. All rights reserved.
2:
18 of 116
(1)
(2)