EM250-DEV Ember, EM250-DEV Datasheet - Page 72

• Manufacturer Part Number: EM250-DEV
• Description: KIT DEV FOR EM250
• Manufacturer: Ember
• Series: InSightr
• Type: 802.15.4/Zigbeer

Specifications of EM250-DEV

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 636-1002

EM250
SC2_DMACTRL [0x4418]
72
SC_TXDMARST
SC_RXDMARST
SC_TXLODB
SC_TXLODA
SC_RXLODB
SC_RXLODA
0-R
0-R
15
0
0
7
120-0082-000I
0-R
0-R
14
0
0
6
[5]
[4]
[3]
[2]
[1]
[0]
SC_TXDMARST
Setting this bit will reset the transmit DMA. The bit is autocleared.
Setting this bit will reset the receive DMA. This bit is autocleared.
Setting this bit loads DMA transmit buffer B addresses and starts the DMA controller process-
ing transmit buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit
will not have any effect. Reading this bit as one indicates DMA processing for buffer B is
active or pending. Reading this bit as zero indicates DMA processing for buffer B is complete
or idle.
Setting this bit loads DMA transmit buffer A addresses and starts the DMA controller process-
ing transmit buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit
will not have any effect. Reading this bit as one indicates DMA processing for buffer A is
active or pending. Reading this bit as zero indicates DMA processing for buffer A is complete
or idle.
Setting this bit loads DMA receive buffer B addresses and starts the DMA controller processing
receive buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer B is active or
pending. Reading this bit as zero indicates DMA processing for buffer B is complete or idle.
Setting this bit loads DMA receive buffer A addresses and starts the DMA controller processing
receive buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer A is active or
pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle.
0-W
0-R
13
0
5
SC_RXDMARST
0-W
0-R
12
0
4
SC_TXLODB
0-RW
0-R
11
0
3
SC_TXLODA
0-RW
0-R
10
0
2
SC_RXLODB
0-RW
0-R
9
0
1
SC_RXLODA
0-RW
0-R
0
8
0