EM250-DEV Ember, EM250-DEV Datasheet - Page 53
![KIT DEV FOR EM250](/photos/14/10/141065/em250-jmp_sml.jpg)
EM250-DEV
Manufacturer Part Number
EM250-DEV
Description
KIT DEV FOR EM250
Manufacturer
Ember
Series
InSightr
Type
802.15.4/Zigbeer
Specifications of EM250-DEV
Frequency
2.4GHz
For Use With/related Products
EM250
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
636-1002
- Current page: 53 of 117
- Download datasheet (2Mb)
SC1_I2CSTAT [0x44A2]
SC1_DMACTRL [0x4498]
SC_I2CCMDFIN
SC_I2CRXFIN
SC_I2CTXFIN
SC_I2CRXNAK
SC_TXDMARST
SC_RXDMARST
SC_TXLODB
SC_TXLODA
SC_RXLODB
SC_RXLODA
0-R
0-R
0-R
0-R
15
15
0
0
0
0
7
7
0-R
0-R
0-R
0-R
14
14
[5]
[4]
[3]
[2]
[1]
[0]
0
0
6
0
0
6
[3]
[2]
[1]
[0]
SC_TXDMARST
This bit is set when a START or STOP command completes. It autoclears on next bus activity.
This bit is set when a byte is received. It autoclears on next bus activity.
This bit is set when a byte is transmitted. It autoclears on next bus activity.
This bit is set when a NACK is received from the slave. It autoclears on next bus activity.
Setting this bit will reset the transmit DMA. The bit is autocleared.
Setting this bit will reset the receive DMA. This bit is autocleared.
Setting this bit loads DMA transmit buffer B addresses and starts the DMA controller processing
transmit buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer B is active or
pending. Reading this bit as zero indicates DMA processing for buffer B is complete or idle.
Setting this bit loads DMA transmit buffer A addresses and starts the DMA controller processing
transmit buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit will
not have any effect. Reading this bit as one indicates DMA processing for buffer A is active or
pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle.
Setting this bit loads DMA receive buffer B addresses and starts the DMA controller processing
receive buffer B. This bit is autocleared when DMA completes. Writing a zero to this bit will not
have any effect. Reading this bit as one indicates DMA processing for buffer B is active or
pending. Reading this bit as zero indicates DMA processing for buffer B is complete or idle.
Setting this bit loads DMA receive buffer A addresses and starts the DMA controller processing
receive buffer A. This bit is autocleared when DMA completes. Writing a zero to this bit will not
have any effect. Reading this bit as one indicates DMA processing for buffer A is active or
pending. Reading this bit as zero indicates DMA processing for buffer A is complete or idle.
0-W
0-R
0-R
0-R
13
13
0
0
5
0
5
SC_RXDMARST
0-W
0-R
0-R
0-R
12
12
0
0
4
0
4
SC_I2CCMDFIN
SC_TXLODB
0-RW
0-R
0-R
0-R
11
11
0
3
0
3
SC_I2CRXFIN
SC_TXLODA
0-RW
0-R
0-R
0-R
10
10
0
2
0
2
SC_I2CTXFIN
SC_RXLODB
0-RW
0-R
0-R
0-R
9
0
1
9
0
1
120-0082-000I
SC_I2CRXNAK
EM250
SC_RXLODA
0-RW
0-R
0-R
0-R
0
0
8
0
8
0
53
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