ISA3 Ember, ISA3 Datasheet
ISA3
Specifications of ISA3
Related parts for ISA3
ISA3 Summary of contents
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... Robust Wi-Fi and Bluetooth coexistence Innovative network and processor debug • Ember InSight port for non-intrusive packet trace with Ember InSight tools • Serial Wire/JTAG interface • Standard ARM debug capabilities: Flash Patch & Breakpoint; Data Watchpoint & ...
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... The EM351 has 128 kB of embedded flash memory and the EM357 has 192 kB of embedded flash memory. Both chips have integrated RAM for data and program storage. The Ember software for the EM35x employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded flash. ...
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Contents 1 Pin Assignments 2 Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 Recommended Operating Conditions 2.3 Environmental Characteristics 2.4 DC Electrical Characteristics 2.5 Digital I/O Specifications 2.6 Non-RF System Electrical Characteristics 2.7 RF Electrical Characteristics 2.7.1 2.7.2 2.7.3 3 Top-Level ...
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Set Up and Configuration 8.3.3 Operation 8.3.4 Interrupts 8.3.5 Registers 8.4 SPI - Slave Mode 8.4.1 GPIO Usage 8.4.2 Set Up and Configuration 8-15 8.4.3 Operation 8.4.4 DMA 8.4.5 Interrupts 8.4.6 Registers 8.5 TWI - Two Wire serial Interfaces ...
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Appendix B Abbreviations and Acronyms Appendix C References EM351 / EM357 Datasheet B-1 C-1 Final 120-035X-000G ...
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Pin Assignments VDD_24MHZ VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF VDD_PADSA PC5, TX_ACTIVE nRESET Refer to Chapter 7, GPIO for details about selecting GPIO pin functions. Figure 1-1. EM35x Pin Assignments ...
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Pin # Signal Direction 1 VDD_24MHZ Power 2 VDD_VCO Power 3 RF_P I/O 4 RF_N I/O 5 VDD_RF Power 6 RF_TX_ALT_P O 7 RF_TX_ALT_N O 8 VDD_IF Power VDD_PADSA Power 11 PC5 I/O TX_ACTIVE O 12 nRESET ...
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Pin # Signal Direction TIM2C3 O (see also Pin 22) TIM2C3 I (see also Pin 22) SC1nCTS I SC1SCLK O SC1SCLK I 20 PB4 I/O TIM2C4 O (see also Pin 24) TIM2C4 I (see also Pin 24) SC1nRTS O SC1nSSEL ...
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Pin # Signal Direction SC2MOSI O SC2MOSI I 22 PA1 I/O TIM2C3 O (see also Pin 19) TIM2C3 I (see also Pin 19) SC2SDA I/O SC2MISO O SC2MISO I 23 VDD_PADS Power 24 PA2 I/O TIM2C4 O (see also Pin ...
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... Select analog function with GPIO_PACFGH[7:4] Data signal of Packet Trace Interface (PTI) Disable trace interface in ARM core Enable PTI in Ember software Select alternate output function with GPIO_PACFGH[7:4] Embedded serial bootloader activation out of reset Signal is active during and immediately after a reset on nRESET. See Section 6 ...
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Pin # Signal Direction TRACEDATA3 O 28 VDD_PADS Power 29 PA6 I/O High current TIM1C3 O TIM1C3 I 30 PB1 I/O SC1MISO O SC1MOSI O SC1SDA I/O SC1TXD O TIM2C1 O (see also Pin 21) TIM2C1 I (see also Pin ...
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Pin # Signal Direction SC1MOSI I SC1SCL I/O SC1RXD I TIM2C2 O (see also Pin 25) TIM2C2 I (see also Pin 25) 32 SWCLK I/O JTCK I 33 PC2 I/O JTDO O SWO O 34 PC3 I/O JTDI I 35 ...
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... ADC reference output Enable analog function with GPIO_PBCFGL[3:0] ADC reference input Enable analog function with GPIO_PBCFGL[3:0] Enable reference output with an Ember system function External interrupt source A Synchronous CPU trace clock Enable trace interface in ARM core Select alternate output function with GPIO_PBCFGL[3:0] ...
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... MHz crystal oscillator or left open when using external clock input on OSCA 24 MHz crystal oscillator or external clock input. External clock input is a 1.8 V square wave. Ground supply pad in the bottom center of the package forms Pin 49. See Ember’s various EM35x Reference Design documentation for PCB considerations. 1-9 Final EM351 / EM357 ...
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Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1 lists the absolute maximum ratings for the EM35x. Parameter Regulator input voltage (VDD_PADS) Analog, Memory and Core voltage (VDD_24MHZ, VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_MEM, VDD_PRE, VDD_SYNTH, VDD_CORE) Voltage on RF_P,N; RF_TX_ALT_P,N ...
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Environmental Characteristics Table 2-3 lists the rated environmental characteristics of the EM35x. Parameter ESD (human body model) ESD (charged device model) ESD (charged device model) Moisture Sensitivity Level (MSL) 2.4 DC Electrical Characteristics Table 2-4 lists the DC electrical ...
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Parameter Reset Current Quiescent current, nRESET asserted Processor and Peripheral Currents ® TM ARM Cortex -M3, RAM, and flash memory ® TM ARM Cortex -M3, RAM, and flash memory ® TM ARM Cortex -M3, RAM, and flash memory sleep current ...
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Parameter Tx Current Radio transmitter, MAC, and baseband Total Tx current ( = I Radio transmitter, MAC and baseband CPU RAM, and Flash memory ) Test Conditions 25°C and 1.8 V core; max. power out (+3 dBm typical) ...
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Figure 2-1 shows the variation of current in transmit mode (with the ARM Figure 2-1. Transmit Power Consumption ® Cortex 2-5 Final EM351 / EM357 TM -M3 running at 12 MHz). 120-035X-000G ...
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... Figure 2-2 shows typical output power against power setting on the Ember reference design. 2.5 Digital I/O Specifications Table 2-5 lists the digital I/O specifications for the EM35x. The digital I/O power (named VDD_PADS) comes from three dedicated pins (Pins 23, 28 and 37). The voltage applied to these pins sets the I/O voltage. ...
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Parameter Input pull-up resistor value Input pull-down resistor value Output voltage for logic 0 Output voltage for logic 1 Output source current (standard current pad) Output sink current (standard current pad) Output source current high current pad: PA6, PA7, PB6, ...
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... Table 2-8 lists the key parameters of the integrated IEEE 802.15.4-2003 receiver on the EM35x. Note: Receive measurements were collected with Ember’s EM35x Ceramic Balun Reference Design (Version A0) at 2440 MHz. The Typical number indicates one standard deviation above the mean, measured at room temperature (25° ...
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Parameter nd 2 high-side adjacent channel rejection nd 2 low-side adjacent channel rejection High-side adjacent channel rejection Low-side adjacent channel rejection nd 2 high-side adjacent channel rejection nd 2 low-side adjacent channel rejection Channel rejection for all other channels 802.11g ...
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... Table 2-9 lists the key parameters of the integrated IEEE 802.15.4-2003 transmitter on the EM35x. Note: Transmit measurements were collected with Ember’s EM35x Ceramic Balun Reference Design (Version A0) at 2440 MHz. The Typical number indicates one standard deviation below the mean, measured at room temperature (25° ...
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Parameter Maximum output power (boost mode) Maximum output power Minimum output power Error vector magnitude (Offset-EVM) Carrier frequency error PSD mask relative PSD mask absolute Figure 2-4 shows the variation of transmit power with temperature for maximum boost mode power, ...
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Synthesizer Table 2-10 lists the key parameters of the integrated synthesizer on the EM35x. Parameter Frequency range Frequency resolution Lock time Relock time Phase noise at 100 kHz offset Phase noise at 1 MHz offset Phase noise at 4 ...
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... IEEE 802.15.4-2003 CSMA-CA algorithm. The EM35x integrates hardware support for a packet trace module, which allows robust packet-based debug. This element is a critical component of InSight Desktop, the Ember software IDE, and provides advanced network debug capability when used with Ember’s InSight Adapter. ...
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... RAM, and flash memories. The 1.25 V regulator output is decoupled externally and supplies the core logic. Note: The EM35x is not pin-compatible with Ember’s previous generation chip, the EM250, except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration to the EM35x. ...
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... Tx Baseband The EM35x Tx baseband in the digital domain spreads the 4-bit symbol into its IEEE 802.15.4-2003-defined 32- chip sequence. It also provides the interface for the Ember software to calibrate the Tx module to reduce silicon process, temperature, and voltage variations. 4.2.2 TX_ACTIVE and nTX_ACTIVE Signals For applications requiring an external PA, two signals are provided called TX_ACTIVE and nTX_ACTIVE ...
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... The EM35x MAC uses a DMA interface to RAM to further reduce the overall ARM When a packet is ready for transmission, the Ember software configures the Tx MAC DMA by indicating the packet buffer RAM location. The MAC waits for the backoff period, then switches the baseband to Tx mode and performs channel assessment ...
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TM 5 ARM Cortex -M3 and Memory Modules This chapter discusses the ARM modules as well as the Memory Protection Unit (MPU). ® TM 5.1 ARM Cortex -M3 Microprocessor The EM35x integrates the ARM EM35x a true System-on-Chip solution. ...
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Embedded Memory Figure 5-1 shows the EM351 ARM memory map. Optional boot mode maps Fixed Info Block to the start of memory Fixed Info Block (2kB) TM ® Cortex -M3 memory map and Figure 5-2 shows the EM357 ARM ...
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Figure 5-2. EM357 ARM 0xE00FFFFF 0xE00FF000 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x42002XXX Register bit band mapped onto System 0x42000000 0x40000XXX mapped onto System 0x40000000 0x22002000 mapped onto System 0x22000000 0x20002FFF mapped onto System 0x20000000 0x08040FFF ...
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... Flash may be programmed either through the Serial Wire/JTAG interface or through bootloader software. Programming flash through Serial Wire/JTAG requires the assistance of RAM-based utility code. Programming through a bootloader requires Ember software for over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also available preprogrammed into the FIB. ...
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Address bits [15:8] 0x08040800 Inverse Option Byte 0 0x08040802 Inverse Option Byte 1 0x08040804 Inverse Option Byte 2 0x08040806 Inverse Option Byte 3 0x08040808 Inverse Option Byte 4 0x0804080A Inverse Option Byte 5 0x0804080C Inverse Option Byte 6 0x0804080E Inverse ...
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... Write protection of address range 0x0802A000 – 0x0802BFFF bit [6] Write protection of address range 0x0802C000 – 0x0802DFFF bit [7] Write protection of address range 0x0802E000 – 0x0802FFFF Option Byte 7 bit [7:0] Reserved for Ember use 1 Option byte 6 is reserved/unused in the EM351 due to the smaller flash size. 5-6 Final EM351 / EM357 120-035X-000G ...
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... Simulated EEPROM Ember software reserves the main flash block as a simulated EEPROM storage area for stack and customer tokens. The simulated EEPROM storage area implements a wear-leveling algorithm to extend the number of simulated EEPROM write cycles beyond the physical limit of 20,000 write cycles for which each flash cell is qualified ...
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... Refer to the ARM Ember software configures the MPU in a standard configuration and application software should not modify it. The configuration is designed for optimal detection of illegal instruction or data accesses illegal access is attempted, the MPU captures information about the access type, the address being accessed, and the location of the offending software ...
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System Modules System modules encompass power domains, resets, clocks, system timers, power management, and encryption. Figure 6-1 shows these modules and how they interact. Figure 6-1. System Module Block Diagram 6-1 Final EM351 / EM357 120-035X-000G ...
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Power domains The EM35x contains three power domains: An “always-on domain” containing all logic and analog cells required to manage the EM35x’s power modes, including the GPIO controller and sleep timer. This domain must remain powered. A “core domain” ...
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Resets The EM35x resets are generated from a number of sources. Each of these reset sources feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of the system ...
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Pin A single active low pin, nRESET, is provided to reset the system. This pin has a Schmitt triggered input. To afford good noise immunity and resistance to switch bounce, the pin is filtered with the Reset Filter ...
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... CPU Lockup is set to indicate that the CPU entered an unrecoverable exception. Execution stops but a reset is not applied. This is so that a debugger can interpret the cause of the error. Ember recommends that in a live application (in other words, no debugger attached) the watchdog be enabled by default so that the EM35x can be restarted ...
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Table 6-5 shows which reset sources generate certain resets. Reset Source POR HV POR LV (due to waking from normal deep sleep) POR LV (not due to waking from normal deep sleep) nRESET Watchdog SYSRESETREQ Option byte error Normal deep ...
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Figure 6-2. Clocks Block Diagram 6-7 Final EM351 / EM357 120-035X-000G ...
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... The high-frequency RC oscillator (OSCHF) is used as the default system clock source when power is applied to the core domain. The nominal frequency coming out of reset is 12 MHz and Ember software calibrates this clock to 12 MHz. Table 6-6 contains the specification for the high frequency RC oscillator. ...
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... A low-frequency RC oscillator (OSCRC) is provided as an internal timing reference. The nominal frequency coming out of reset is 10 kHz, and Ember software calibrates this clock to 10 kHz. From the tuned 10 kHz oscillator (OSCRC) Ember software calibrates a fractional-N divider to produce a 1 kHz reference clock, CLK1K. ...
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Table 6-9 contains the specification for the low frequency crystal oscillator. Table 6-9. Low-Frequency Crystal Oscillator Specification Parameter Frequency Accuracy Load capacitance OSC32A Load capacitance OSC32B Crystal ESR Start-up time Current consumption 6.3.5 Clock Switching The EM35x has two switching ...
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... In the situation where the chip performs a deep sleep that maintains the system time and is woken up from an external event (that is, not a sleep timer event), the deep sleep module in the Ember software delays until the next sleep timer clock tick ( ms) to guarantee that the sleep timer updates correctly. ...
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Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and the sleep timer is active. Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is ...
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... In the deep sleep state the EM35x waits for a wake up event which will return it to the running state. In powering up the core logic the ARM ® stack and application state to the point where deep sleep was invoked. TM Cortex -M3 is put through a reset cycle and Ember software restores the 6-13 Final EM351 / EM357 120-035X-000G ...
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... Physically connecting or disconnecting a debugger from the chip will not alter the state of these signals. A debugger must logically communicate with the SWJ-DP to set or clear these two signals. For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact Ember support for Application Notes and ARM ® ...
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Registers PERIPHERAL_DISABLE Peripheral Disable Register PERIDIS_RSVD Bitname Bitfield PERIDIS_RSVD [5] PERIDIS_ADC [4] PERIDIS_TIM2 [3] PERIDIS_TIM1 [2] PERIDIS_SC1 [1] PERIDIS_SC2 [0] 6.6 Security Accelerator ...
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GPIO (General Purpose Input / Output) The EM35x has 24 multi-purpose GPIO pins, which may be individually configured as: General purpose output General purpose open-drain output Alternate output controlled by a peripheral device Alternate open-drain output controlled by a ...
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Each of the three GPIO ports has the following registers whose low-order eight bits correspond to the port’s eight GPIO pins: GPIO_PxIN (input data register) returns the pin level (unless in analog mode). GPIO_PxOUT (output data register) controls the output ...
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... The alternate outputs of PA4 and PA5 can either provide packet trace data (PTI_EN and PTI_DATA), or synchronous CPU trace data (TRACEDATA2 and TRACEDATA3). The selection of packet trace or CPU trace is made through the Ember software GPIO does not have an associated peripheral in alternate output mode, its output is set to 0. ...
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JTAG mode is forced when the EM35x resets, a designer must treat all four debug GPIOs as working in unison even though the Serial Wire interface only uses one of the GPIO, PC4. Note: An application must disable all ...
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... PA4, PA5, PB5, PB6, PB7, and PC1 can be analog inputs to the ADC. PB0 can be an external analog voltage reference input to the ADC can output the internal analog voltage reference from the ADC. The Ember software selects an internal or external voltage reference. PC6 and PC7 can connect to an optional 32.768 kHz crystal. ...
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Input Mode Input mode is used both for general purpose input and for on-chip peripheral inputs. Input floating mode disables the internal pull-up and pull-down resistors, leaving the pin in a high-impedance state. Input pull-up or pull-down mode enables ...
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... GPIO: any change in logic value triggers a wake event.) Hardware records the fact that GPIO activity caused a wake event, but not which specific GPIO was responsible. Instead, Ember’s software reads the state of the GPIOs on waking to determine this. ...
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GPIO_IRQxSEL some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for example to generate an interrupt from the slave select ...
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GPIO Analog Alternate Output 1 PA0 TIM2C1 , SC2MOSI 1 PA1 TIM2C3 , SC2MISO, SC2SDA 1 PA2 TIM2C4 , SC2SCLK, SC2SCL 1 PA3 TIM2C2 , TRACECLK PA4 ADC4 PTI_EN, TRACEDATA2 PA5 ADC5 PTI_DATA, TRACEDATA3 PA6 TIM1C3 3 PA7 TIM1C4, REG_EN ...
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Registers GPIO_PxCFGL GPIO_PACFGL Port A Configuration Register (Low) GPIO_PBCFGL Port B Configuration Register (Low) GPIO_PCCFGL Port C Configuration Register (Low) Substitute for x in the following detail description ...
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GPIO_PxCFGH GPIO_PACFGH Port A Configuration Register (High) GPIO_PBCFGH Port B Configuration Register (High) GPIO_PCCFGH Port C Configuration Register (High) Substitute for x in the following detail description ...
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GPIO_PxIN GPIO_PAIN Port A Input Data Register GPIO_PBIN Port B Input Data Register GPIO_PCIN Port C Input Data Register Substitute for x in the following detail description ...
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GPIO_PxOUT GPIO_PAOUT Port A Output Data Register GPIO_PBOUT Port B Output Data Register GPIO_PCOUT Port C Output Data Register Substitute for x in the following detail description ...
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GPIO_PxCLR GPIO_PACLR Port A Output Clear Register GPIO_PBCLR Port B Output Clear Register GPIO_PCCLR Port C Output Clear Register Substitute for x in the following detail description ...
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GPIO_PxSET GPIO_PASET Port A Output Set Register GPIO_PBSET Port B Output Set Register GPIO_PCSET Port C Output Set Register Substitute for x in the following detail description ...
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GPIO_PxWAKE GPIO_PAWAKE Port A Wakeup Monitor Register GPIO_PBWAKE Port B Wakeup Monitor Register GPIO_PCWAKE Port C Wakeup Monitor Register Substitute for x in the following detail description ...
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GPIO_WAKEFILT GPIO Wakeup Filtering Register Bitname Bitfield IRQD_WAKE_FILTER [3] SC2_WAKE_FILTER [2] SC1_WAKE_FILTER [1] GPIO_WAKE_FILTER [ ...
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GPIO_IRQxSEL GPIO_IRQCSEL Interrupt C Select Register GPIO_IRQDSEL Interrupt D Select Register Substitute the detailed description below Bitname Bitfield SEL_GPIO [4:0] ...
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GPIO_INTCFGx GPIO_INTCFGA GPIO Interrupt A Configuration Register GPIO_INTCFGB GPIO Interrupt B Configuration Register GPIO_INTCFGC GPIO Interrupt C Configuration Register GPIO_INTCFGD GPIO Interrupt D Configuration Register Substitute for x in the following detail description ...
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INT_GPIOFLAG GPIO Interrupt Flag Register Bitname Bitfield INT_IRQDFLAG [3] INT_IRQCFLAG [2] INT_IRQBFLAG [1] INT_IRQAFLAG [ ...
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GPIO_DBGCFG GPIO Debug Configuration Register GPIO_DEBUGDIS Bitname Bitfield GPIO_DEBUGDIS [5] GPIO_EXTREGEN [4] GPIO_DBGCFGRSVD [ ...
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GPIO_DBGSTAT GPIO Debug Status Register Bitname Bitfield GPIO_BOOTMODE [3] GPIO_FORCEDBG [1] GPIO_SWEN [ ...
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Serial Controllers 8.1 Overview The EM35x has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications. SPI (Serial Peripheral Interface), master or slave TWI (Two Wire serial Interface), master only UART ...
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Configuration Before using a serial controller, configure and initialize it as follows: Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.). Configure the GPIO pins used by the serial controller as ...
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Registers SCx_MODE SC1_MODE Serial Mode Register SC2_MODE Serial Mode Register Bitname Bitfield SC_MODE [1: ...
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INT_SCxFLAG INT_SC1FLAG Serial Controller 1 Interrupt Flag Register INT_SC2FLAG Serial Controller 2 Interrupt Flag Register INT_SC1PARERR INT_SC1FRMERR 7 6 INT_SCCMDFIN INT_SCTXFIN Bitname Bitfield INT_SC1PARERR [14] INT_SC1FRMERR [13] INT_SCTXULDB [12] ...
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INT_SCxCFG INT_SC1CFG Serial Controller 1 Interrupt Configuration Register INT_SC2CFG Serial Controller 2 Interrupt Configuration Register INT_SC1PARERR INT_SC1FRMERR 7 6 INT_SCCMDFIN INT_SCTXFIN Bitname Bitfield INT_SC1PARERR [14] INT_SC1FRMERR [13] INT_SCTXULDB [12] ...
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SCx_INTMODE SC1_INTMODE Serial Controller 1 Interrupt Mode Register SC2_INTMODE Serial Controller 2 Interrupt Mode Register Bitname Bitfield SC_TXIDLELEVEL [2] SC_TXFREELEVEL [1] SC_RXVALLEVEL [0] 8.3 ...
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The GPIO pins used for these signals are shown in Table 8-3. Additional outputs may be needed to drive the nSSEL signals on slave devices. Direction GPIO Configuration Alternate Output SC1 pin SC2 pin 8.3.2 Set Up and Configuration Both ...
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SCx_SPICFG 1 SC_SPIxxx MST ORD PHA POL Same as above except data is sent LSB first instead of MSB first ...
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SC_SPIRPT bit in the SCx_SPICFG register. This functionality can only be enabled or disabled when the transmit FIFO is empty and the transmit serializer is ...
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Registers SCx_DATA SC1_DATA Serial Data Register SC2_DATA Serial Data Register Bitname Bitfield SC_DATA [7: ...
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SCx_SPICFG SC1_SPICFG SPI Configuration Register SC2_SPICFG SPI Configuration Register Bitname Bitfield SC_SPIRXDRV [5] SC_SPIMST [4] SC_SPIRPT [3] SC_SPIORD [2] SC_SPIPHA [1] SC_SPIPOL [0] 29 ...
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SCx_SPISTAT SC1_SPISTAT SPI Status Register SC2_SPISTAT SPI Status Register Bitname Bitfield SC_SPITXIDLE [3] SC_SPITXFREE [2] SC_SPIRXVAL [1] SC_SPIRXOVF [ ...
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SCx_RATELIN SC1_RATELIN Serial Clock Linear Prescaler Register SC2_RATELIN Serial Clock Linear Prescaler Register Bitname Bitfield SC_RATELIN [3: ...
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SCx_RATEEXP SC1_RATEEXP Serial Clock Exponential Prescaler Register SC2_RATEEXP Serial Clock Exponential Prescaler Register Bitname Bitfield SC_RATEEXP [3:0] 8.4 SPI - Slave Mode Both SC1 ...
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The GPIO pins that can be assigned to these signals are shown in Table 8-5. MOSI Input Direction GPIO Configuration Input SC1 pin PB2 PA0 SC2 pin 8.4.2 Set Up and Configuration Both serial controllers, SC1 and SC2, support SPI ...
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The SPI slave controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-6). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the SCx_SPICFG registers. SCx_SPICFG 1 SC_SPIxxx ...
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FIFO is drained. Once the DMA marks a receive error, two conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded. ...
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Registers Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_SPICFG, and SCx_SPISTAT registers. 8.5 TWI - Two Wire serial Interfaces Both EM35x serial controllers SC1 and SC2 include a Two Wire serial ...
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EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register. Table 8-8 shows the rate settings for Standard-Mode TWI (100 kbps) and Fast-Mode TWI (400 kbps) operation. Table 8-8. TWI Clock ...
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Table 8-9. TWI Master Frame Segments SCx_TWICTRL1 1 SC_TWIxxxx Frame Segments START SEND RECV STOP pending frame segment 1 ...
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Full TWI frames have to be constructed by software from individual TWI segments. All necessary segment transitions are shown in Figure 8-2. ACK or NACK generation of a TWI receive frame segment is determined with the SC_TWIACK bit in the ...
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Character transmitted ( transition of SC_TWITXFIN) Character received ( transition of SC_TWIRXFIN) Received and lost character while receive FIFO was full (receive overrun error) Transmitted character while transmit FIFO was empty (transmit underrun error) To enable ...
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SCx_TWICTRL1 SC1_TWICTRL1 TWI Control Register 1 SC2_TWICTRL1 TWI Control Register Bitname Bitfield SC_TWISTOP [3] SC_TWISTART [2] SC_TWISEND [1] SC_TWIRECV [ ...
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SCx_TWICTRL2 SC1_TWICTRL2 TWI Control Register 2 SC2_TWICTRL2 TWI Control Register Bitname Bitfield SC_TWIACK [0] 8.6 UART - Universal Asynchronous Receiver / Transmitter The ...
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The GPIO pins assigned to these signals are shown in Table 8-10. TXD Direction Output Alternate GPIO Configuration Output (push-pull) PB1 SC1 pin 1 only used if RTS/CTS hardware flow control is enabled. 8.6.2 Set Up and Configuration The UART ...
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The UART is best operated in systems where the other side of the communication link also uses a crystal as its timing reference, and baud rates should be selected to minimize the baud rate mismatch to the crystal tolerance. Additionally, ...
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Figure 8-3. UART Character Frame Format TXD Start Data Data or Idle time Bit Bit 0 Bit 1 RXD 8.6.3 FIFOs Characters transmitted and received by the UART are buffered in the transmit and receive FIFOs that are both 4 ...
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If the SC_UARTAUTO bit is set, nRTS is controlled automatically by hardware: nRTS is put into the low state (asserted) when the receive FIFO has room for at least two characters, otherwise the high state (unasserted). If ...
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Registers Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA register. SC1_UARTSTAT UART Status Register SC_UARTTXIDLE SC_UARTPARERR Bitname ...
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SC1_UARTCFG UART Configuration Register SC_UARTAUTO SC_UARTFLOW Bitname Bitfield SC_UARTAUTO [6] SC_UARTFLOW [5] SC_UARTODD [4] SC_UARTPAR [3] SC_UART2STP [2] SC_UART8BIT [1] SC_UARTRTS [ ...
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SC1_UARTPER UART Baud Rate Period Register Bitname Bitfield SC_UARTPER [15: SC_UARTPER 5 4 ...
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SC1_UARTFRAC UART Baud Rate Fractional Period Register Bitname Bitfield SC_UARTFRAC [0] 8.7 DMA Channels The EM35x serial DMA channels enable efficient, high-speed operation of ...
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A DMA buffer’s end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while the buffer is loaded or active. This is useful for receiving messages that contain an initial byte count, since it allows software to set the buffer end address ...
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Registers SCx_DMACTRL SC1_DMACTRL Serial DMA Control Register SC2_DMACTRL Serial DMA Control Register SC_TXDMARST Bitname Bitfield SC_TXDMARST [5] SC_RXDMARST [4] SC_TXLODB [3] SC_TXLODA [2] ...
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SCx_DMASTAT SC1_DMASTAT Serial DMA Status Register SC2_DMASTAT Serial DMA Status Register SC_RXPARB SC_RXPARA Bitname Bitfield SC_RXSSEL [12:10] SC_RXFRMB [9] SC_RXFRMA [8] SC_RXPARB [7] SC_RXPARA [6] SC_RXOVFB ...
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SCx_TXBEGA SC1_TXBEGA Transmit DMA Begin Address Register A SC2_TXBEGA Transmit DMA Begin Address Register Bitname Bitfield SC_TXBEGA [13: ...
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SCx_TXBEGB SC1_TXBEGB Transmit DMA Begin Address Register B SC2_TXBEGB Transmit DMA Begin Address Register Bitname Bitfield SC_TXBEGB [13: ...
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SCx_TXENDA SC1_TXENDA Transmit DMA End Address Register A SC2_TXENDA Transmit DMA End Address Register Bitname Bitfield SC_TXENDA [13: ...
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SCx_TXENDB SC1_TXENDB Transmit DMA End Address Register B SC2_TXENDB Transmit DMA End Address Register Bitname Bitfield SC_TXENDB [13: ...
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SCx_TXCNT SC1_TXCNT Transmit DMA Count Register SC2_TXCNT Transmit DMA Count Register Bitname Bitfield SC_TXCNT [13: ...
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SCx_RXBEGA SC1_RXBEGA Receive DMA Begin Address Register A SC2_RXBEGA Receive DMA Begin Address Register Bitname Bitfield SC_RXBEGA [13: ...
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SCx_RXBEGB SC1_RXBEGB Receive DMA Begin Address Register B SC2_RXBEGB Receive DMA Begin Address Register Bitname Bitfield SC_RXBEGB [13: ...
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SCx_RXENDA SC1_RXENDA Receive DMA End Address Register A SC2_RXENDA Receive DMA End Address Register Address: 0x4000C004 Reset: 0x20000000 Bitname Bitfield SC_RXENDA [13: ...
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SCx_RXENDB SC1_RXENDB Receive DMA End Address Register B SC2_RXENDB Receive DMA End Address Register Bitname Bitfield SC_RXENDB [13: ...
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SCx_RXCNTA SC1_RXCNTA Receive DMA Count Register A SC2_RXCNTA Receive DMA Count Register Bitname Bitfield SC_RXCNTA [13: ...
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SCx_RXCNTB SC1_RXCNTB Receive DMA Count Register B SC2_RXCNTB Receive DMA Count Register Bitname Bitfield SC_RXCNTB [13: ...
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SCx_RXCNTSAVED SC1_RXCNTSAVED Saved Receive DMA Count Register SC2_RXCNTSAVED Saved Receive DMA Count Register Bitname Bitfield SC_RXCNTSAVED [13: ...
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SCx_RXERRA SC1_RXERRA DMA First Receive Error Register A SC2_RXERRA DMA First Receive Error Register Bitname Bitfield SC_RXERRA [13: ...
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SCx_RXERRB SC1_RXERRB DMA First Receive Error Register B SC2_RXERRB DMA First Receive Error Register Bitname Bitfield SC_RXERRB [13: ...
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General Purpose Timers (TIM1 and TIM2) 9.1 Introduction Each of the EM35x’s two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse ...
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Figure 9-1. General-Purpose Timer Block Diagram Note: The internal signals shown in Figure 9-1 are described in the Timer Signal Descriptions section, and are used throughout the text to describe how the timer components are interconnected. 9-2 Final 120-035X-000G ...
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GPIO Usage The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs. As with all EM35x digital inputs, a GPIO used as a timer input can be shared with other uses of ...
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TIMx_CR1 register. The UEV is generated when both the counter reaches the overflow (or underflow when down-counting) and when the TIM_UDIS bit equals 0 in the TIMx_CR1 ...
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INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupts when clearing the counter on the capture event. When a UEV occurs, the update flag (the INT_TIMUIF bit in the ...
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Figure 9-5. Counter Timing Diagram, Update Event when TIM_ARBE = 0 (TIMx_ARR not buffered) Figure 9-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-Counting Mode 9.3.2.2 In down-counting mode, the counter counts from the auto-reload value ...
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When a UEV occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_USR is 1) and the following registers are updated: The prescaler shadow register is reloaded with the buffer value (contents of the TIMx_PSC ...
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In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupt when ...
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Figure 9-11. Counter Timing Diagram, Update Event with TIM_ARBE = 1 (counter overflow) 9.3.3 Clock Selection The counter clock can be provided by the following clock sources: Internal clock (PCLK) External clock mode 1: external input pin (TIy) External clock ...
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Figure 9-13. TI2 External Clock Connection Example For example, to configure the up-counter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input: ...
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Table 9-2. TIM_EXTRIGSEL Clock Signal Selection TIM_EXTRIGSEL bits Clock Signal Selection 00 PCLK (peripheral clock). When running from the 24 MHz crystal oscillator, the PCLK frequency is 12 MHz. When the 12 MHz RC oscillator is in use, the frequency ...
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Figure 9-16. Control Circuit in External Clock Mode 2 9.3.4 Capture/Compare Channels Each capture/compare channel is built around a capture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an output stage ...
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Figure 9-18. Capture/Compare Channel 1 Main Circuit Figure 9-19 show details of the output stage of a capture/compare channel. Figure 9-19. Output Stage of Capture/Compare Channel (Channel 1) The capture/compare block is made of a buffer register and a shadow ...
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If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture flag INT_TIMMISSCCyIF in the INT_TIMxMISS register is set. INT_TIMCCyIF can be cleared by software writing its bit or reading the captured data ...
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Select the active input for TIMx_CCR2by writing the TIM_CC2S bits the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP2 (used for capture in the TIMx_CCR2) by writing the TIM_CC2P bit to 1 (active on falling ...
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Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG register). Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in the INT_TIMxCFG register). The TIMx_CCRy registers can be programmed with or ...
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Because the buffer registers are only transferred to the shadow registers when a UEV occurs, before starting the counter initialize all the registers by setting the TIM_UG bit in the TIMx_EGR register. OCy polarity is software programmable using the TIM_CCyP ...
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PWM Center-Aligned Mode 9.3.9.3 Center-aligned mode is active except when the TIM_CMS bits in the TIMx_CR1 register are 00 (all configurations where TIM_CMS is non-zero have the same effect on the OCyREF/OCy signals). The compare flag is set when the ...
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Hints on using center-aligned mode: When starting in center-aligned mode, the current up-down configuration is used. This means that the counter counts up or down depending on the value written in the TIM_DIR bit in the TIMx_CR1 register. The TIM_DIR ...
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Figure 9-24 illustrates this example. Figure 9-24. Example of One Pulse Mode 9.3.10.1 A Special Case: OCy Fast Enable In one-pulse mode, the edge detection on the TIy input sets the TIM_CEN bit, which enables the counter. Then the comparison ...
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Table 9-3. Counting Direction versus Encoder Signals Active Edges Level on Opposite Signal (TI1FP1 for TI2, TI2FP2 for TI1) Counting on TI1 High only Low Counting on TI2 High only Low Counting on TI1 High and TI2 Low An external ...
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Figure 9-26 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except TIM_CC1P = 1). Figure 9-26. Example of Encoder Interface Mode with IC1FP1 Polarity Inverted The timer configured in encoder interface mode provides ...
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The counter starts counting on the internal clock, then behaves normally until the TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (the INT_TIMTIF bit in the ...
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Slave Mode: Trigger Mode 9.3.13.3 In trigger mode the counter starts in response to an event on a selected input. In the following example, the up-counter starts in response to a rising edge on the TI2 input: Configure channel 2 ...
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A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due ...
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Using One Timer to Enable the Other Timer 9.3.14.2 In this example, shown in Figure 9-32, the enable of Timer 2 is controlled with the output compare 1 of Timer 1. Timer 2 counts on the divided internal clock only ...
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Figure 9-33. Gating Timer 2 with Enable of Timer 1 9.3.14.3 Using One Timer to Start the Other Timer In this example (see Figure 9-34), the enable of Timer 2 is set with the UEV of Timer 1. Timer 2 ...
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Figure 9-35. Triggering Timer 2 with Enable of Timer 1 Starting both Timers Synchronously in Response to an External Trigger 9.3.14.4 This example sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2 ...
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Figure 9-36. Triggering Timer 1 and 2 with Timer 1 TI1 Input 9.3.15 Timer Signal Descriptions Table 9-4. Timer Signal Descriptions Signal Internal/ Description External CK_INT Internal Internal clock source: connects to EM35x peripheral clock (PCLK) in internal clock mode. ...
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Interrupts Each timer has its own top-level NVIC interrupt. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. Chapter 11, Interrupt ...
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Registers TIMx_CR1 TIM1_CR1 Timer 1 Control Register 1 TIM2_CR1 Timer 2 Control Register TIM_ARBE TIM_CMS Bitname Bitfield TIM_ARBE [7] TIM_CMS [6:5] TIM_DIR [4] TIM_OPM ...
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Bitname Bitfield TIM_CEN [0] Access Description RW Counter Enable. 0: Counter disabled. 1: Counter enabled. Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has been previously set by software. Trigger mode sets the ...
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TIMx_CR2 TIM1_CR2 Timer 1 Control Register 2 TIM2_CR2 Timer 2 Control Register TIM_TI1S Bitname Bitfield TIM_TI1S [7] TIM_MMS [6: ...
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TIMx_SMCR TIM1_SMCR Timer 1 Slave Mode Control Register TIM2_SMCR Timer 2 Slave Mode Control Register TIM_ETP TIM_ECE 7 6 TIM_MSM Bitname Bitfield TIM_ETP [15] TIM_ECE [14] TIM_ETPS [13:12 ...
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Bitname Bitfield TIM_ETF [11:8] TIM_MSM [7] TIM_TS [6:4] TIM_SMS [2:0] Access Description RW External Trigger Filter. This defines the frequency used to sample the ETRP signal, Fsampling, and the length of the digital filter applied to ETRP. The digital filter ...
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TIMx_EGR TIM1_EGR Timer 1 Event Generation Register TIM2_EGR Timer 2 Event Generation Register TIM_TG Bitname Bitfield TIM_TG [6] TIM_CC4G [4] TIM_CC3G [3] TIM_CC2G [2] TIM_CC1G ...
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TIM1_CCMR1 TIM1_CCMR1 Timer 1 Capture/Compare Mode Register 1 TIM2_CCMR1 Timer 2 Capture/Compare Mode Register TIM_IC2F TIM_IC1F Timer channels can be programmed as inputs (capture mode) ...
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Bitname Bitfield TIM_OC2FE [10] TIM_IC2F [15:12] TIM_IC2PSC [11:10] TIM_CC2S [9:8] TIM_OC1M [6:4] TIM_OC1BE [3 TIM_OC1FE [2] TIM_IC1F [7:4] TIM_IC1PSC [3:2] Access Description RW Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0.) This bit speeds the effect of ...
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Bitname Bitfield TIM_CC1S [1:0] Access Description RW Capture / Compare 1 Selection. This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input ...
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TIMx_CCMR2 TIM1_CCMR2 Timer 1 Capture/Compare Mode Register 2 TIM2_CCMR2 Timer 2 Capture/Compare Mode Register TIM_IC4F TIM_IC3F Timer channels can be programmed as inputs (capture mode) ...
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Bitname Bitfield TIM_OC4FE [10] TIM_IC4F [15:12] TIM_IC4PSC [11:10] TIM_CC4S [9:8] TIM_OC3M [6:4] TIM_OC3BE [3 TIM_OC3FE [2] TIM_IC3F [7:4] TIM_IC3PSC [3:2] Access Description RW Output Compare 4 Fast Enable. (Applies only if TIM_CC4S = 0.) This bit speeds the effect of ...
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Bitname Bitfield TIM_CC3S [1:0] Access Description RW Capture / Compare 3 Selection. This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input ...
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TIMx_CCER TIM1_CCER Timer 1 Capture/Compare Enable Register TIM2_CCER Timer 2 Capture/Compare Enable Register Bitname Bitfield TIM_CC4P [13] TIM_CC4E [12] TIM_CC3P [9] TIM_CC3E [8] TIM_CC2P ...
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TIMx_CNT TIM1_CNT Timer 1 Counter Register TIM2_CNT Timer 2 Counter Register Bitname Bitfield TIM_CNT [15: ...
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TIMx_PSC TIM1_PSC Timer 1 Prescaler Register TIM2_PSC Timer 2 Prescaler Register Bitname Bitfield TIM_PSC [3: ...
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TIMx_ARR TIM1_ARR Timer 1 Auto-Reload Register TIM2_ARR Timer 2 Auto-Reload Register Bitname Bitfield TIM_ARR [15: ...
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TIMx_CCR1 TIM1_CCR1 Timer 1 Capture/Compare Register 1 TIM2_CCR1 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...
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TIMx_CCR2 TIM1_CCR2 Timer 1 Capture/Compare Register 2 TIM2_CCR2 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...
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TIMx_CCR3 TIM1_CCR3 Timer 1 Capture/Compare Register 3 TIM2_CCR3 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...
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TIMx_CCR4 TIM1_CCR4 Timer 1 Capture/Compare Register 4 TIM2_CCR4 Timer 2 Capture/Compare Register Bitname Bitfield TIM_CCR [15: ...
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TIM1_OR Timer 1 Option Register Bitname Bitfield TIM_ORRSVD [3] TIM_CLKMSKEN [2] TIM1_EXTRIGSEL [1: ...
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TIM2_OR Timer 2 Option Register TIM_REMAPC4 TIM_REMAPC3 Bitname Bitfield TIM_REMAPC4 [7] TIM_REMAPC3 [6] TIM_REMAPC2 [5] TIM_REMAPC1 [4] TIM_ORRSVD [3] TIM_CLKMSKEN [2] TIM1_EXTRIGSEL [1: ...
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INT_TIMxCFG INT_TIM1CFG Timer 1 Interrupt Configuration Register INT_TIM2CFG Timer 2 Interrupt Configuration Register INT_TIMTIF Bitname Bitfield INT_TIMTIF [6] INT_TIMCC4IF [4] INT_TIMCC3IF [3] INT_TIMCC2IF [2] INT_TIMCC1IF ...
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INT_TIMxFLAG INT_TIM1FLAG Timer 1 Interrupt Flag Register INT_TIM2FLAG Timer 2 Interrupt Flag Register INT_TIMTIF Bitname Bitfield INT_TIMRSVD [12:9] INT_TIMTIF [6] INT_TIMCC4IF [4] INT_TIMCC3IF [3] INT_TIMCC2IF ...
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INT_TIMxMISS INT_TIM1MISS Timer 1 Missed Interrupt Register INT_TIM2MISS Timer 2 Missed Interrupts Register Bitname Bitfield INT_TIMMISSCC4IF [12] INT_TIMMISSCC3IF [11] INT_TIMMISSCC2IF [10] INT_TIMMISSCC1IF [9] INT_TIMMISSRSVD [6:0] ...
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... Single-ended conversions are performed by connecting one of the differential inputs to VREF/2 while fully differential operation uses two external inputs. Note: The regulator input voltage, VDD_PADS, cannot be measured using the ADC, but it can be measured through Ember software. 10.1 Setup and Configuration To use the ADC follow this procedure, described in more detail in the next sections: Configure any GPIO pins to be used by the ADC in analog mode ...
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... PB0. To output the internal VREF on PB0, the ADC must be enabled (ADC_ENABLE bit set in the ADC_CFG register) and PB0 must be configured in analog mode. To use an external reference, the Ember software must be called after reset and after waking from deep sleep. PB0 must also be configured in analog mode using GPIO_PBCFGH[3:0]. See the Ember software documentation for more information on using an external reference ...
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Reset initializes the offset to zero (ADC_OFFSET = 0) and gain factor to one (ADC_GAIN = 0x8000). 10.1.4 DMA The ADC DMA channel writes converted data, which incorporates the offset/gain correction, into a DMA buffer in RAM. The ADC DMA ...
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ADC_MUXn Analog source at ADC 0 ADC0 1 ADC1 2 ADC2 3 ADC3 4 ADC4 5 ADC5 6 No connection 7 No connection 8 GND 9 VREF/2 10 VREF 11 VDD_PADSA connection 13 No connection 14 No ...
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Input Range The single-ended input range is fixed VREF and the differential input range is fixed as -VREF to +VREF. 10.1.5.3 Sample Time ADC sample time is programmed by selecting the sampling clock and the ...
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INT_ADCULDFULL – the DMA wrote to the last location in the buffer (DMA buffer full). INT_ADCULDHALF – the DMA wrote to the last location of the first half of the DMA buffer (DMA buffer half full). INT_ADCDATA – there is ...
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... Offset error is calculated from the minimum input and gain error is calculated from the full scale input range. Correction using VREF is recommended because VREF is calibrated by the Ember software against VDD_PADSA. The VDD_PADSA regulator is factory-trimmed to 1.80 V ± 20 mV. If better absolute accuracy is required, the ADC can be configured to use an external reference. The ADC calibrates as a single-ended measurement ...
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VGND cannot be measured when the input buffer is enabled because it is outside the buffer’s input range sampling of VREF. Due to the ADC's internal design, VREF does not yield ...
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Parameter SNR (dB) 35 Single-Ended 35 Differential SINAD (dB) 35 Single-Ended 35 Differential SDFR (dB) 59 Single-Ended 60 Differential THD (dB) -45 Single-Ended -45 Differential ENOB (from SNR) Single-Ended 5.6 Differential 5.6 ENOB (from SINAD) Single-Ended 5.5 Differential 5.6 Equivalent ...
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Parameter 0.026 DNL (codes peak) 0.007 DNL (codes RMS) 5.6 ENOB (from single-cycle test) SNR (dB) Single-Ended Differential SINAD (dB) Single-Ended Differential SDFR (dB) Single-Ended Differential THD (dB) Single-Ended -45 Differential -45 ENOB (from SNR) Single-Ended 5.6 Differential 5.6 ENOB ...
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Parameter 3 dB Cut-off (kHz) 56.6k 0.055 INL (codes peak) 0.028 INL (codes RMS) 0.028 DNL (codes peak) 0.01 DNL (codes RMS) 3.6 ENOB (from single-cycle test) SNR (dB) Single-Ended 23 Differential 23 SINAD (dB) Single-Ended 23 Differential 23 SDFR ...
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Parameter VREF output current VREF load capacitance External VREF voltage range External VREF input impedance Minimum input voltage Maximum input voltage Single-ended signal range Differential signal range Common mode range Input referred ADC offset Input Impedance 1 MHz sample clock ...
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Registers ADC_DATA ADC Data Register Bitname Bitfield ADC_DATA_FIELD [15: ADC_DATA_FIELD 5 4 ...
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ADC_CFG ADC Configuration Register ADC_PERIOD 7 6 ADC_MUXP Bitname Bitfield ADC_PERIOD [15:13] ADC_CFGRSVD2 [12:11] ADC_MUXP [10:7] ADC_MUXN [6:3] ADC_1MHZCLK [2] ADC_CFGRSVD [1] ADC_ENABLE [ ...
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ADC_OFFSET ADC Offset Register Bitname Bitfield ADC_OFFSET_FIELD [15: ADC_OFFSET_FIELD ADC_OFFSET_FIELD ...
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ADC_GAIN ADC Gain Register Bitname Bitfield ADC_GAIN_FIELD [15: ADC_GAIN_FIELD ADC_GAIN_FIELD ...
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ADC_DMACFG ADC DMA Configuration Register Bitname Bitfield ADC_DMARST [4] ADC_DMAAUTOWRAP [1] ADC_DMALOAD [ ...
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ADC_DMASTAT ADC DMA Status Register Bitname Bitfield ADC_DMAOVF [1] ADC_DMAACT [ ...
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ADC_DMABEG ADC DMA Begin Address Register Bitname Bitfield ADC_DMABEG [13: ...
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ADC_DMASIZE ADC DMA Buffer Size Register Bitname Bitfield ADC_DMASIZE_FIELD [12: ...
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ADC_DMACUR ADC DMA Current Address Register Bitname Bitfield ADC_DMACUR_FIELD [13: ADC_DMACUR_FIELD ...