EM250-DEV Ember, EM250-DEV Datasheet - Page 44

• Manufacturer Part Number: EM250-DEV
• Description: KIT DEV FOR EM250
• Manufacturer: Ember
• Series: InSightr
• Type: 802.15.4/Zigbeer

Specifications of EM250-DEV

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 636-1002

EM250
44
120-0082-000I
indication: setting the appropriate
priate DMA buffer after it has unloaded.
Receiving a character always requires transmitting a character. In a case when a long stream of receive char-
acters is expected, a long sequence of (dummy) transmit characters must be generated. To avoid software or
transmit DMA initiating these transfers (and consuming unnecessary bandwidth), the SPI serializer can be in-
structed to retransmit the last transmitted character, or to transmit a busy token (
by the register bit
when the transmit FIFO is empty and the transmit serializer is idle, as indicated by a cleared
register bit in the
Every time an automatic character transmission is started, a transmit underrun is detected (as there is no data
in transmit FIFO), and the register bit
abling the automatic character transmission, the reception of new characters stops and the receive FIFO holds
characters just received.
Note: The event Receive DMA complete does not automatically mean receive FIFO empty.
Interrupts are generated on the following events:
To generate interrupts to the CPU, the interrupt masks in the
abled.
5.2.3
The SC1 I
3. The I
not implemented, so multiple master applications are not supported. The I
signals, and external pull-up resistors are required.
The SC1 I
The following signals can be made available on the GPIO pins:
The I
by a clock division ratio from the 24MHz clock:
EXP is written to the
tings for Standard I
Transmit FIFO empty and last character shifted out (0 to 1 transition of
Transmit FIFO changed from full to not full (0 to 1 transition of
Receive FIFO changed from empty to not empty (0 to 1 transition of
Transmit DMA buffer A/B complete (1 to 0 transition of
Receive DMA buffer A/B complete (1 to 0 transition of
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
Programmable clock frequency (400kHz max.)
Supports both 7-bit and 10-bit addressing
MSDA (serial data)
MSCL (serial clock)
Nominal Rate = 24MHz / ( 2 * (LIN + 1) * 2
2
C Master controller obtains its reference clock from a programmable clock generator. Clock rates are set
2
I
C Master controller supports Standard (100kbps) and Fast (400kbps) I
2
2
2
C Master Mode
C controller is only available in master mode. The SC1 I
C mode has the following features:
SC1_SPISTAT
SC_SPIRPT
2
C (100kbps) and Fast I
SC1_RATEEXP
in the
register.
SC_TX/RXDMARST
register and LIN to the
SC1_SPICFG
INT_SCTXUND
2
C (400kbps) operation.
EXP
)
register. This functionality can only be enabled (or disabled)
in the
bit in the
SC_RXACTA/B
SC1_RATELIN
INT_SC1FLAG
SC_TXACTA/B
INT_SC1CFG
SC1_DMACTRL
2
C controller is enabled with
SC_SPITXFREE
)
SC_SPIRXVAL
register. Table 22 shows the rate set-
)
register is set. Note that after dis-
2
and
C signals are pure open-collector
SC_SPITXIDLE
2
C modes. Address arbitration is
register, or loading the appro-
INT_CFG
0xFF
)
)
), which is determined
registers must be en-
)
SC_SPITXIDLE
SC1_MODE
set to