EM250-DEV Ember, EM250-DEV Datasheet - Page 62

• Manufacturer Part Number: EM250-DEV
• Description: KIT DEV FOR EM250
• Manufacturer: Ember
• Series: InSightr
• Type: 802.15.4/Zigbeer

Specifications of EM250-DEV

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 636-1002

EM250
62
2
2
2
2
2
2
2
1
1
1
1
1
1
1
120-0082-000I
SC2_SPICFG
1
-
-
0
0
0
0
0
0
1
1
-
-
-
Serialized SC2 SPI transmit data is driven to the output pin MOSI. SC2 SPI master data is received from the in-
put pin MISO. To generate slave select signals to SPI slave devices, other GPIO pins have to be used and their
assertion must be controlled by software.
Characters transmitted and received are passed through transmit and receive FIFOs. The transmit and receive
FIFOs are 4 bytes deep. These FIFOs are accessed under software control by accessing the
ister or under hardware control using a DMA controller.
When a transmit character is written to the (empty) transmit FIFO, the register bit
SC2_SPISTAT
acters can be written to the transmit FIFO until it is full, which causes the register bit
SC2_SPISTAT
mit character becomes available in the transmit FIFO. This causes the register bit
SC2_SPISTAT
the register bit
Any character received is stored in the (empty) receive FIFO. The register bit
SC2_SPISTAT
software or DMA is not reading from the receive FIFO, the receive FIFO will store up to 4 characters. Any fur-
ther reception is dropped and the register bit
hardware generates the
til the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear the error
0
1
0
1
-
-
-
SC2-3M mode
SC2-3M mode
SC2-3M mode
SC2-3M mode
SC2-3M mode
SC2-4S mode
SC2-2 mode
register clears and indicates that not all characters are transmitted yet. Further transmit char-
register to clear. After shifting out one transmit character to the MOSI pin, space for one trans-
register to get set. After all characters are shifted out, the transmit FIFO empties, which causes
register is set to indicate that not all received characters are read out from receive FIFO. If
SC_SPITXIDLE
INT_SCRXOVF
Frame Format
Same as above except LSB first instead of MSB first
Illegal
Illegal
MSCLK
MSCLK
MSCLK
MSCLK
in the
MOSI
MOSI
MOSI
MOSI
MISO
MISO
MISO
MISO
Table 24. SC2 SPI Master Mode Formats
out
out
out
out
out
out
out
out
in
in
in
in
SC2_SPISTAT
interrupt, but the DMA register will not indicate the error condition un-
RX[7]
RX[7]
RX[7]
RX[7]
TX[7]
TX[7]
TX[7]
TX[7]
SC_SPIRXOVF
register to get set also.
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
RX[6]
TX[6]
in the
TX[5]
RX[5]
TX[5]
RX[5]
TX[5]
RX[5]
TX[5]
RX[5]
SC2_SPISTAT
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
TX[4]
RX[4]
RX[3]
RX[3]
RX[3]
TX[3]
RX[3]
TX[3]
TX[3]
TX[3]
SC_SPIRXVAL
register is set. The RX FIFO
SC_SPITXFREE
RX[2]
RX[2]
RX[2]
RX[2]
TX[2]
TX[2]
TX[2]
TX[2]
SC_SPITXIDLE
SC_SPITXFREE
RX[1]
RX[1]
RX[1]
RX[1]
SC2_DATA
TX[1]
TX[1]
TX[1]
TX[1]
in the
RX[0]
RX[0]
RX[0]
RX[0]
TX[0]
TX[0]
TX[0]
TX[0]
in the
in the
data reg-
in the