AD8339ACPZ Analog Devices Inc, AD8339ACPZ Datasheet - Page 6

• Manufacturer Part Number: AD8339ACPZ
• Description: IC I/Q DEMOD QUAD 50MHZ 40-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD8339ACPZ

• Function: Demodulator
• Lo Frequency: 0Hz ~ 200MHz
• Rf Frequency: 0Hz ~ 50MHz
• P1db: 14.8dBm
• Gain: -1.3dB
• Noise Figure: 11.5dB
• Current - Supply: 35mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 40-VFQFN, 40-CSP, Exposed Pad
• Frequency Range: DC To 50MHz
• Rf Type: Quadrature
• Supply Voltage Range: ± 4.5V To ± 5.5V
• Rf Ic Case Style: LFCSP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8339-EVALZ - BOARD EVAL AD8339 I/Q DEMOD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8339
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1, 2, 9, 10, 13,
14, 37, 38
3, 4, 15, 36
5
6
7, 8, 11, 16,
27, 28, 35
12
17
18, 19, 21, 22,
29, 30, 32, 33
20, 23, 24, 31
25, 26
34
39
40
EP
Mnemonic
RF1P to RF4P,
RF1N to RF4N
COMM
SCLK
CSB
VPOS
SDO
LODC
I1OP to I4OP,
Q1OP to Q4OP
VNEG
4LON, 4LOP
RSET
SDI
RSTS
Description
RF Inputs. Require external 2.5 V bias for optimum symmetrical input differential swing if ±5 V supplies
are used.
Ground.
Serial Interface Clock.
Serial Interface Chip Select Bar. Active low.
Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply and a
0.1 μF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected,
one set of supply decoupling components on each side of the chip should be sufficient.
Serial Interface Data Output. Normally connected to the SDI pin of the next chip or left open.
Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. The value
of this capacitor affects the chip enable/disable times.
I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a
transimpedance amplifier. Multiple outputs can be summed by simply connecting them (wire-OR). The
bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 53).
Negative Supply. These pins should be decoupled with a ferrite bead in series with the supply and a
0.1 μF capacitor between the VNEG pins and ground. Because the VNEG pins are internally connected,
one set of supply decoupling components for the chip should be sufficient.
LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs
should be driven differentially. If driven by a single-ended sine wave at 4LOP or 4LON, the signal level
should be >0 dBm (50 Ω) with external bias resistors.
Reset for LO Interface. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic.
Serial Interface Data Input. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS
logic.
Reset for SPI Interface. Logic threshold is at ~1.5 V with ±0.3 V hysteresis and should be driven by >3.3 V
CMOS logic. For quick testing without the need to program the SPI, the voltage on the RSTS pin should
be pulled to −1.4 V; this enables all four channels in the phase (I = 1, Q = 0) state.
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the ground plane.
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE GROUND PLANE.
COMM
COMM
VPOS
VPOS
SCLK
RF2N
RF3N
RF2P
RF3P
CSB
1
2
3
4
5
6
7
8
9
10
40
11
Figure 2. Pin Configuration
39
12
Rev. A | Page 6 of 36
PIN 1
INDICATOR
38
13
(Not to Scale)
37
14
AD8339
TOP VIEW
36
15 16
35
34 33
17
18
32
19
31
20
30
29
28
27
26
25
24
23
22
21
Q2OP
I2OP
VPOS
VPOS
4LOP
4LON
VNEG
VNEG
I3OP
Q3OP