AD8339ACPZ Analog Devices Inc, AD8339ACPZ Datasheet - Page 19

• Manufacturer Part Number: AD8339ACPZ
• Description: IC I/Q DEMOD QUAD 50MHZ 40-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD8339ACPZ

• Function: Demodulator
• Lo Frequency: 0Hz ~ 200MHz
• Rf Frequency: 0Hz ~ 50MHz
• P1db: 14.8dBm
• Gain: -1.3dB
• Noise Figure: 11.5dB
• Current - Supply: 35mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 40-VFQFN, 40-CSP, Exposed Pad
• Frequency Range: DC To 50MHz
• Rf Type: Quadrature
• Supply Voltage Range: ± 4.5V To ± 5.5V
• Rf Ic Case Style: LFCSP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8339-EVALZ - BOARD EVAL AD8339 I/Q DEMOD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

QUADRATURE GENERATION
The internal 0° and 90° LO phases are digitally generated by a
divide-by-4 logic circuit. The divider is dc-coupled and inherently
broadband; the maximum LO frequency is limited only by its
switching speed. The duty cycle of the quadrature LO signals
is intrinsically 50% and is unaffected by the asymmetry of the
externally connected 4LO input. Furthermore, the divider is
implemented such that the 4LO signal reclocks the final flip-
flops that generate the internal LO signals and thereby minimizes
noise introduced by the divide circuitry.
For optimum performance, the 4LO input is driven differentially,
but it can also be driven single-ended. A good choice for a drive
is an LVDS device as is done on the AD8339 evaluation board.
The common-mode range on each pin is approximately 0.2 V to
3.8 V with the nominal ±5 V supplies.
The minimum 4LO level is frequency dependent when driven
by a sine wave. For optimum noise performance, it is important
to ensure that the LO source has very low phase noise (jitter)
and adequate input level to ensure stable mixer core switching.
The gain through the divider determines the LO signal level vs.
RF frequency. The AD8339 can be operated at very low frequen-
cies at the LO inputs if a square wave is used to drive the LO, as
is done with the LVDS driver on the evaluation board.
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. A
reset pin is provided to synchronize the LO divider circuits in
different AD8339s when they are used in arrays. The RSET pin
resets the dividers to a known state after power is applied to
multiple AD8339s. A logic input must be provided to the RSET
pin when using more than one AD8339. Note that at least one
channel must be enabled for the LO interface to also be enabled
and the LO reset to work. See the Reset Input section for more
information.
I/Q DEMODULATOR AND PHASE SHIFTER
The I/Q demodulators consist of double-balanced Gilbert cell
mixers. The RF input signals are converted into currents by
transconductance stages that have a maximum differential input
signal capability of 2.8 V p-p. These currents are then presented
to the mixers, which convert them to baseband (RF − LO) and
twice RF (RF + LO). The signals are phase shifted according to
the codes programmed into the SPI latch (see Table 4); the
phase bits are labeled PHx0 through PHx3, where 0 indicates
LSB and 3 indicates MSB. The phase shift function is an integral
part of the overall circuit (patent pending). The phase shift
listed in Column 1 of Table 4 is defined as being between the
baseband I or Q channel outputs. As an example, for a common
signal applied to a pair of RF inputs to an AD8339, the baseband
outputs are in phase for matching phase codes. However, if the
phase code for Channel 1 is 0000 and that of Channel 2 is 0001,
then Channel 2 leads Channel 1 by 22.5°.
Rev. A | Page 19 of 36
Following the phase shift circuitry, the differential current
signal is converted from differential to single-ended via a
current mirror. An external transimpedance amplifier is needed
to convert the I and Q outputs to voltages.
Table 4. Phase Select Code for Channel-to-Channel Phase Shift
Φ Shift
0°
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
DYNAMIC RANGE AND NOISE
Figure 53 is an interconnection block diagram of all four channels
of the AD8339. More channels are easily added to the summation
(up to 16 when using an
by wire-OR connecting the outputs as shown for four channels.
For optimum system noise performance, the RF input signal is
provided by a very low noise amplifier, such as the LNA of the
AD8332, AD8334, or AD8335. In beamforming applications,
the I and Q outputs of a number of receiver channels are summed
(for example, the four channels illustrated in Figure 53). The
dynamic range of the system increases by the factor 10 log
where N is the number of channels (assuming random uncorre-
lated noise). The noise in the 4-channel example of Figure 53 is
increased by 6 dB while the signal quadruples (12 dB), yielding
an aggregate SNR improvement of 6 dB (12 − 6).
Judicious selection of the RF amplifier ensures the least degrada-
tion in dynamic range. The input referred spectral voltage noise
density (e
noise of the AD8339 to degrade the system noise figure (NF) by
1 dB, the combined noise of the source and the LNA should be
approximately twice that of the AD8339, or 22 nV/√Hz. If the
noise of the circuitry before the AD8339 is less than 22 nV/√Hz,
the system NF degrades more than 1 dB. For example, if the
noise contribution of the LNA and source is equal to the AD8339,
or 11 nV/√Hz, the degradation is 3 dB. If the circuit noise
preceding the AD8339 is 1.3× as large as that of the AD8339 (or
~14 nV/√Hz), the degradation is 2 dB. For a circuit noise 1.45×
that of the AD8339 (16 nV/√Hz), the degradation is 1.5 dB.
n
) of the AD8339 is nominally ~11 nV/√Hz. For the
PHx3 (MSB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AD8021
PHx2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
as the summation amplifier)
PHx1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AD8339
PHx0 (LSB)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10
(N),