HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 738
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
16.5
IICI is the interrupt source of IIC. Table 16.6 shows each interrupt source and its priority. The
ICCR interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt
controller.
Table 16.6 IIC Interrupt Source
Channel
0
1
16.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 16.7 shows the timing of SCL and SDA output in synchronization with the internal
Rev. 6.00 Mar. 18, 2010 Page 676 of 982
REJ09B0054-0600
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read PORT in each I
output pin, and check that SCL and SDA are both low. Even if the ICE bit is set to 1, it is
possible to monitor the pin state by reading the PORT register so long as the DDR I/O port
register corresponding to the pin has been cleared to 0. Then issue the instruction that
generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared
to 0.
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRT to ICDRS)
ICDRS to ICDRR)
Interrupt Source
Usage Notes
2
Name
IICI0
IICI1
C Bus Interface (IIC) (Option)
Enable Bit
IEIC
IEIC
Interrupt Source
request
request
I
I
2
2
C bus interface interrupt
C bus interface interrupt
Interrupt
Flag
IRIC
IRIC
2
C bus, neither
Interrupt
Priority
High
Low
2
C bus
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