HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 337
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.6
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.12
shows the interrupt sources and their priority order.
Table 8.12 Interrupt Sources and Priority Order
Interrupt
Name
DEND0A
DEND0B
DEND1A
DEND1B
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 8.12.
Figure 8.37 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.
Interrupt Sources
Figure 8.37 Block Diagram of Transfer End/Transfer Break Interrupt
DTE/
DTME
DTIE
Interrupt Source
Short Address Mode
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0B
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1B
Full Address Mode
Interrupt due to end of
transfer on channel 0
Interrupt due to break in
transfer on channel 0
Interrupt due to end of
transfer on channel 1
Interrupt due to break in
transfer on channel 1
Rev. 6.00 Mar. 18, 2010 Page 275 of 982
Section 8 DMA Controller (DMAC)
Transfer end/transfer
break interrupt
Interrupt
Priority Order
High
Low
REJ09B0054-0600
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