HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 554
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Note: * See section 14.1.3 (1), Slave Status Read (Control Bits: H'0, H'6).
(c) Acknowledge Bit at the End of the Message Length Field
(d) Acknowledge Bit at the End of the Data Field
Note: * In this case, data field is transferred repeatedly until the number of data reaches the
Rev. 6.00 Mar. 18, 2010 Page 492 of 982
REJ09B0054-0600
⎯ When bit 3 in the control bits is 1 (data write) although the slave receive buffer* is not
⎯ When the control bits are set to the data read (H'3, H'7) although the slave transmit buffer*
⎯ When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or
⎯ When the control bits are the locked address read (H'4, H'5) although the unit is not locked
⎯ When a timing error occurs
⎯ When the control bits are undefined
The acknowledge bit at the end of the message length field becomes NAK in the following
cases and transfer is stopped.
⎯ When the parity of the message length bits is incorrect
⎯ When a timing error occurs
The acknowledge bit at the end of the data field becomes NAK in the following cases and
transfer is stopped.
⎯ When the parity of the data bits is incorrect*
⎯ When a timing error occurs after the previous transfer of the acknowledge bit
⎯ When the receive buffer becomes full and cannot accept further data
empty
is empty
H'F in the control bits although the slave unit has been locked
maximum number of transfer bytes if the number of data does not exceed the
maximum number of transfer bytes in one frame.
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