HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 714
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
Bit
0
Note:
Rev. 6.00 Mar. 18, 2010 Page 652 of 982
REJ09B0054-0600
Bit Name
ACKB
* Only a 0 can be written to this bit, to clear the flag.
2
C Bus Interface (IIC) (Option)
Initial
Value
0
R/W
R/W
Description
Acknowledge Bit
Stores acknowledge data.
Transmit mode:
[Setting condition]
When 1 is received as the acknowledge bit when ACKE = 1
in transmit mode
[Clearing conditions]
•
•
Receive mode:
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus line
(returned by the receiving device) is read in transmission
(when TRS = 1). In reception (when TRS = 0), the value set
by internal software is read.
When this bit is written, acknowledge data that is returned
after receiving is rewritten regardless of the TRS value. If bit
in ICSR is written using bit-manipulation instructions, the
acknowledge data should be re-set since the acknowledge
data setting is rewritten by the ACKB bit reading value.
Write the ACKE bit to 0 to clear the ACKB flag to 0, before
transmission is ended and a stop condition is issued in
master mode, or before transmission is ended and SDA is
released to issue a stop condition by a master device.
When 0 is received as the acknowledge bit when ACKE =
1 in transmit mode
When 0 is written to the ACKE bit
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