HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 667
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Figure 15.20 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
No
No
No
[3]
[2]
[1]
Section 15 Serial Communication Interface (SCI)
Notes: 1. Supported only by the
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
Rev. 6.00 Mar. 18, 2010 Page 605 of 982
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC *
the DTC *
data empty interrupt (TXI) request and
data is written to TDR.
2. The case, in which the DTC
H8S/2239 Group.
automatically clears the TDRE
flag, occurs only when DISEL in
DTC is 0 with the transfer
counter not being 0. Therefore,
the TDRE flag should be
cleared by CPU when DISEL is
1, or when DISEL is 0 with the
transfer counter being 0.
2
is activated by a transmit
REJ09B0054-0600
1
or
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