HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 318
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 318 of 1048
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Section 8 DMA Controller (DMAC)
8.5.8
An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev. 6.00 Mar. 18, 2010 Page 256 of 982
REJ09B0054-0600
Basic Bus Cycles
Address bus
CPU cycle
HWR
LWR
Figure 8.18 Example of DMA Transfer Bus Timing
RD
φ
T
1
address
Source
T
2
DMAC cycle (1-word transfer)
T
1
T
2
Destination address
T
3
T
1
T
2
T
3
CPU cycle
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