HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 256
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Bus Controller
7.7.2
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.6.4, Wait
Control.
Wait states cannot be inserted in a burst cycle.
7.8
When this LSI accesses external space, it can insert a 1-state idle cycle (T
the following two cases: (1) when read accesses between different areas occur consecutively, and
(2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, with a long output floating time, and
high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
Rev. 6.00 Mar. 18, 2010 Page 194 of 982
REJ09B0054-0600
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an
idle cycle is inserted at the start of the second read cycle.
Figure 7.21 shows an example of the operation in this case. In this example, bus cycle A is a
read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from
SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a
collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an
idle cycle is inserted, and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
Data bus
Wait Control
Idle Cycle
RD
φ
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
T
Figure 7.21 Example of Idle Cycle Operation (1)
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
T
2
I
) between bus cycles in
T
3
T
Bus cycle B
I
T
1
T
2
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