HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 221
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.2.2
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3
BCRA controls channel A PC breaks.
Bit
7
6
5
4
3
2
1
Bit Name
CMFA
CDA
BAMRA2
BAMRA1
BAMRA0
CSELA1
CSELA0
Break Address Register B (BARB)
Break Control Register A (BCRA)
Initial Value
0
0
0
0
0
0
0
R/W
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
1
Description
Condition Match Flag A
[Setting condition]
When a condition set for channel A is satisfied
[Clearing condition]
When 0 is written to CMFA after reading*
= 1
CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU, DTC, or DMAC *
Break Address Mask Register A2 to A0
These bits specify which bits of the break address
set in BARA are to be masked.
000: BAA23 to 0 (All bits are unmasked)
001: BAA23 to 1 (Lowest bit is masked)
010: BAA23 to 2 (Lower 2 bits are masked)
011: BAA23 to 3 (Lower 3 bits are masked)
100: BAA23 to 4 (Lower 4 bits are masked)
101: BAA23 to 8 (Lower 8 bits are masked)
110: BAA23 to 12 (Lower 12 bits are masked)
111: BAA23 to 16 (Lower 16 bits are masked)
Break Condition Select
Selects break condition of channel A.
00: Instruction fetch
01: Data read cycle
10: Data write cycle
11: Data read/write cycle
Rev. 6.00 Mar. 18, 2010 Page 159 of 982
Section 6 PC Break Controller (PBC)
3
REJ09B0054-0600
2
CMFA
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