HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 1029
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Port Name
Pin Name
PG0/IRQ6
Legend:
H:
L:
T:
keep:
DDR:
OPE:
WAITE: Wait input enable
BRLE: Bus release enable
Notes: 1. The port state is L (address input) in modes 4 and 5.
PF0/BREQ/
IRQ2
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/
IRQ7
High level
Low level
The input port becomes high-impedance, and the output port retains its state
Data direction register
Output port enable
2. Not available in the H8S/2237 Group and H8S/2227 Group.
3. Supported only by the H8S/2239 Group.
4. Not available in the H8S/2227 Group.
High-impedance
MCU
Operating
Mode
4 to 7
4 to 6
7
4, 5
6
7
4 to 6
7
Power-On
Reset
T
T
T
H
T
T
T
T
Manual
Reset
keep
keep
keep
keep
keep
keep
keep
Hardware
Standby
Mode
T
T
T
T
T
T
T
Appendix A I/O Port States in Each Pin State
Rev. 6.00 Mar. 18, 2010 Page 967 of 982
Software
Standby
Mode,
Watch Mode
keep
[BRLE = 0]
keep
[BRLE = 1]
T
keep
[DDR ⋅ OPE
= 0]
T
[DDR ⋅ OPE
= 1]
H
keep
[DDR ⋅ OPE
= 0]
T
[DDR ⋅ OPE
= 1]
H
keep
Bus
Mastership
Release
State
keep
T
keep
T
keep
T
keep
REJ09B0054-0600
Program
Execution
State,
Sleep Mode,
Subsleep
Mode
[BRLE = 0]
I/O port
[BRLE = 1]
BREQ
I/O port
[DDR = 0]
I/O port
[DDR = 1]
CS0
(H in sleep
mode and
subsleep
mode.)
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
I/O port
I/O port
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