HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 550
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
The slave unit returns the acknowledgement when the slave addresses match and the parities of the
master and slave addresses are correct. When either of the parities of the master and slave
addresses is wrong, the slave unit decides that the master or slave address is not correctly received
and does not return the acknowledgement. In this case, the master unit enters the waiting (monitor)
state, and communications end.
In the case of broadcast communications, the slave address is used to identify the type of broadcast
communications (group or general) as follows:
• When the slave address is H'FFF: General broadcast communications
• When the slave address is other than H'FFF: Group broadcast communications
Note: The group number is the upper 4-bit value of the slave address in group broadcast
communications.
(4) Control Field
The control field is a field for transmitting the type and direction of the following data field. The
control field is comprised of control bits, a parity bit, and an acknowledge bit.
The control bits include four bits and are output MSB first.
The parity bit is output following the control bits. When the parity is correct, and the slave unit
can implement the function required from the master unit, the slave unit returns the
acknowledgement and enters the message length field output state. However, if the slave unit
cannot implement the requirements from the master unit even though the parity is correct, or if the
parity is not correct, the slave unit does not return the acknowledgement, and returns to the waiting
(monitor) state.
The master unit enters the subsequent message length field output state after confirming the
acknowledgement.
When the acknowledgement is not confirmed, the master unit enters the waiting (monitor) state,
and communications end. However, in the case of broadcast communications, the master unit
enters the following message length field output state without confirming the acknowledgement.
For details of the contents of the control bit, see table 14.4.
Rev. 6.00 Mar. 18, 2010 Page 488 of 982
REJ09B0054-0600
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