HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 47

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

2.1.3
System registers consist of four 32-bit registers: multiply and accumulate registers high and low
(MACH and MACL), procedure register (PR), and program counter (PC). The multiply and
accumulate registers store the results of multiply and accumulate operations. The procedure
register stores the return address for a subroutine procedure. The program counter stores program
addresses to control the flow of the processing.
2.1.4
Table 2.1 lists the values of the registers after reset.
Table 2.1
Classification
General registers R0–R14
Control registers
System registers
31
31
31
Initial Values of Registers
System Registers
(Sign extended)
Initial Values of Registers
Register
R15 (SP)
SR
GBR
VBR
MACH, MACL, PR
PC
MACL
PR
PC
9
Figure 2.3 System Registers
MACH
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I3–I0 are 1111(H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address table
0
0
0
Multiply and accumulate (MAC) registers
high and low (MACH, MACL): Store the
results of multiply and accumulate opera-
tions. MACH is sign-extended when read
because only the lowest 10 bits are valid.
Procedure register (PR): Stores the return
address for a subroutine procedure.
Program counter (PC): Indicates the
fourth byte (second instruction) after
the current instruction.
Rev. 7.00 Jan 31, 2006 page 19 of 658
REJ09B0272-0700
Section 2 CPU