HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 384

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
Table 13.2 Registers
Channel
0
1
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
13.2
13.2.1
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR
in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form.
When one byte has been received, it is automatically transferred to the receive data register
(RDR). The CPU cannot read or write to RSR directly.
13.2.2
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into RDR for
Rev. 7.00 Jan 31, 2006 page 356 of 658
REJ09B0272-0700
Bit
Read/Write
2. Only 0 can be written, to clear flags.
Register Descriptions
Receive Shift Register
Receive Data Register
details on the register addresses, see section 8.3.5, Area Descriptions.
Address *
H'05FFFEC0
H'05FFFEC1
H'05FFFEC2
H'05FFFEC3
H'05FFFEC4
H'05FFFEC5
H'05FFFEC8
H'05FFFEC9
H'05FFFECA
H'05FFFECB
H'05FFFECC Serial status register
H'05FFFECD Receive data register
1
—
7
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register TDR0
Serial status register
Receive data register
Serial mode register
Bit rate register
Serial control register
Transmit data register TDR1
—
6
—
5
SMR0
SCR0
SSR0
SMR1
SCR1
SSR1
Abbreviation
BRR0
RDR0
BRR1
RDR1
—
4
—
3
R/W
R/W
R/W
R/W
R/(W) *
R/W
R/W
R/W
R/W
R/(W) *
R/W
R
R
—
2
2
2
H'00
H'FF
H'00
H'FF
H'00
H'FF
H'00
H'FF
Initial
Value
H'84
H'00
H'84
H'00
—
1
Access
size
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
—
0