HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 138

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Bit 13—Warp Mode Bit (WARP): WARP selects warp or normal mode. 0 sets normal mode and
1 sets warp mode. In warp mode, some external accesses are carried out in parallel with internal
access.
Bit 13: WARP
0
1
Bit 12—RD Duty (RDDTY): RDDTY selects 35% or 50% of the T1 state as the high-level duty
cycle ratio of signal RD. 0 sets 50%, 1 sets 35%.
Bit 12: RDDTY
0
1
Bit 11—Byte Access Select (BAS): BAS selects whether byte access control signals are WRH,
WRL, and A0, or LBS, WR and HBS during word space accesses. When this bit is cleared to 0,
WRH, WRL, and A0 signals are valid; when set to 1, LBS, WR, and HBS signals are valid.
Bit 11: BAS
0
1
Bits 10–0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 7.00 Jan 31, 2006 page 110 of 658
REJ09B0272-0700
Description
Normal mode: External and internal accesses are not performed
simultaneously
Warp mode: External and internal accesses are performed simultaneously
Description
RD signal high-level duty cycle is 50% of T1 state
RD signal high-level duty cycle is 35% of T1 state
Description
WRH, WRL, and A0 enabled
LBS, WR, and HBS enabled
(Initial value)
(Initial value)
(Initial value)