HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 248

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
9.5
1. All registers other than the DMA operation register (DMAOR) and DMA channel control
2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when
3. Even when an NMI interrupt is input when the DMAC is not operating, the NMIF bit in
4. Interrupt during DMAC transfer
5. The CPU and DMAC leave the bus released and the operation of the chip is stopped when the
Rev. 7.00 Jan 31, 2006 page 220 of 658
REJ09B0272-0700
registers 0–3 (CHCR0–CHCR3) should be accessed in word or longword units.
rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance).
DMAOR will be set.
When an interrupt occurs during DMAC transfer, the following operation takes place.
a. When an NMI interrupt is input, the DMAC stops operation and returns the bus to the
b. When an interrupt other than an NMI occurs
following conditions are satisfied
Remedy: Clear the warp bit in BCR to 0 to set normal mode.
CPU. The CPU then executes the interrupt handling.
The warp bit (WARP) in the bus control register (BCR) of the bus controller (BSC) is set
The DMAC is in cycle-steal transfer mode
The CPU accesses (reads/writes) the on-chip I/O space
Usage Notes
When the DMAC is in burst mode
The DMAC does not return the bus to the CPU in burst mode. Therefore, even when an
interrupt is requested in DMAC operation, the CPU cannot acquire the bus with, the
result that interrupt handling is not executed. When the DMAC completes the transfer
and the CPU acquires the bus, the CPU executes interrupt handling if the interrupt
requested during DMAC transfer is not cleared.*
Note: * Clear conditions for an interrupt request:
When the DMAC is in cycle-steal mode
The DMAC returns the bus to the CPU every time the DMAC completes a transfer unit
in cycle-steal mode. Therefore, the CPU executes the requested interrupt handling when
it acquires the bus.
When an interrupt is requested from an on-chip supporting module, and the interrupt
When an interrupt is requested by IRQ (edge detection), and the CPU begins
When an interrupt is requested by IRQ (level detection), and the IRQ interrupt
source flag is cleared
interrupt handling for the IRQ request source
request signal returns to the high level