HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 215

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 11:
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SCI0, SCI1: Serial communication interface channels 0 and 1
ITU0–ITU3: Channels 0–3 of the 16-bit integrated timer pulse unit
Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be
2. Transfer from memory-mapped external device or external memory to external device
3. Transfer from external device with DACK to memory-mapped external device or
4. Dual address mode.
Bit 10:
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
selected in channels 2 and 3.
with DACK.
external memory.
Bit 9:
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 8:
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
DREQ (External request *
Reserved (illegal setting)
DREQ (External request *
DREQ (External request *
RXI0 (On-chip serial communication interface 0 receive data
full interrupt transfer request) *
TXI0 (On-chip serial communication interface 0 transmit data
empty interrupt transfer request) *
RXI1 (On-chip serial communication interface 1 receive data
full interrupt transfer request) *
TXI1 (On-chip serial communication interface 1 transmit data
empty interrupt transfer request) *
IMIA0 (On-chip ITU0 input capture/compare match A interrupt
transfer request) *
IMIA1 (On-chip ITU1 input capture/compare match A interrupt
transfer request) *
IMIA2 (On-chip ITU2 input capture/compare match A interrupt
transfer request) *
IMIA3 (On-chip ITU3 input capture/compare match A interrupt
transfer request) *
Auto-request (Transfer requests automatically generated
within DMAC) *
ADI (A/D conversion end interrupt request of on-chip A/D
converter) *
Reserved (illegal setting)
Reserved (illegal setting)
Section 9 Direct Memory Access Controller (DMAC)
4
4
4
4
4
4
Rev. 7.00 Jan 31, 2006 page 187 of 658
1
1
1
, dual address mode) (Initial value)
, single address mode *
, single address mode *
4
4
4
4
REJ09B0272-0700
2
3
)
)