C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 88

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The
IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the
IT0 and IT1 bits in TCON
table below lists the possible configurations.
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.15). Note that /INT0 and
/INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their
assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port
pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the
associated bit in register XBR0 (see
on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-
pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level
sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity
bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the
input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of
the ISR completes or another interrupt request will be generated.
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter-
rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each
interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure its priority level. Low prior-
ity is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced
first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 9.4.
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:
1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending
when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the
new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the
next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock
cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL
to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be
serviced until the current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during FLASH write/erase operations and USB FIFO MOVX accesses (see
“12.2. Accessing USB FIFO Space” on page
while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service proce-
dure (as described above) and the amount of time the CPU is stalled.
88
IT0
1
1
0
0
IN0PL
0
1
0
1
/INT0 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
(Section “19.1. Timer 0 and Timer 1” on page
Section “14.1. Priority Crossbar Decoder” on page 129
114). Interrupt service latency will be increased for interrupts occuring
Rev. 1.1
IT1
1
1
0
0
217) select level or edge sensitive. The
IN1PL
0
1
0
1
/INT1 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
for complete details
Section