C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 152

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 15.3 for a list of
maximum packet sizes for each FIFO configuration.
15.5.3. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register
unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When
an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT
endpoint FIFO; a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO.
152
R/W
Bit7
Endpoint
Number
USB Addresses 0x20 - 0x23 provide access to the 4 pairs of endpoint FIFOs:
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint.
IN/OUT Endpoint FIFO
Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers)
0
1
2
3
R/W
Bit6
Split Mode
Enabled?
0
1
2
3
N/A
R/W
Bit5
N
Y
N
Y
N
Y
Table 15.3. FIFO Configurations
Maximum IN Packet Size
(Double Buffer Disabled /
Enabled)
USB Address
R/W
Bit4
FIFODATA
0x20
0x21
0x22
0x23
256 / 128
128 / 64
Rev. 1.1
64 / 32
R/W
Bit3
R/W
Bit2
256 / 128
512 / 256
128 / 64
64
Maximum OUT Packet Size
(Double Buffer Disabled /
Enabled)
R/W
Bit1
256 / 128
128 / 64
64 / 32
R/W
Bit0
0x20 - 0x23
USB Address:
00000000
Reset Value