C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 232

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
19.3.3. USB Start-of-Frame Capture
When T3SOF = ‘1’, Timer 3 operates in USB Start-of-Frame (SOF) capture mode. When T3SPLIT = ‘0’, Timer 3
counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents of the Timer 3 reg-
isters (TMR3H:TMR3L) are latched into the Timer 3 Reload registers (TMR3RLH:TMR3RLL). A Timer 3 interrupt
is generated if enabled. This mode can be used to calibrate the system clock or external oscillator against the known
USB host SOF clock.
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter counts up
independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents of the Timer 3 reg-
isters are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A Timer 3 interrupt is generated if
enabled.
232
Figure 19.22. Timer 3
External Clock / 8
‘0’)
SYSCLK / 12
(T3SPLIT
Capture
External Clock / 8
T
F
H
Mode
3
=
T
F
3
L
TMR3CN
T
F
3
L
E
N
SYSCLK / 12
SOF
O
T
3
S
F
SYSCLK
T
3
S
P
L
T
I
R
T
3
H
T
F
3
T
F
3
L
X
C
K
T
3
L
0
1
TMR3CN
E
N
T
F
3
L
T
S
O
F
3
T
S
P
T
3
L
I
T
R
3
SYSCLK
C
T
3
X
L
K
0
1
Figure 19.23. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’)
Start-of-Frame
M
T
3
H
0
1
1
0
M
T
3
L
0
1
(SOF)
USB
CKCON
M
H
T
2
M
H
T
3
M
T
2
L
M
T
3
L
M
T
1
CKCON
M
H
T
2
M
T
0
M
T
2
L
TR3
S
C
A
1
TR3
M
T
1
S
C
A
0
M
T
0
Rev. 1.1
S
C
A
1
S
C
A
0
Enable
TCLK
TCLK
Capture
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
TMR3RLL TMR3RLH
TMR3L
Interrupt
Capture
Capture
TMR3H
To ADC
Start-of-Frame
(SOF)
Enable
USB
To ADC
Interrupt