C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 104

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
104
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-
modify-write instructions read and modify the source enable only. This applies to bits: USBRSF, C0RSEF,
SWRSF, MCDRSF, PORSF.
USBRSF
R/W
Bit7
USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
FERROR: FLASH Error Indicator.
0: Source of last reset was not a FLASH read/write/erase error.
1: Source of last reset was a FLASH read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset source.
1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source (active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing Clock
Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock Detector
enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On / VDD Monitor Reset Flag.
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD monitor as
a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled and stabilized can
cause a system reset. See register VDM0CN (Figure 10.3).
0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a reset
source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate; Write:
VDD monitor is a reset source.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not /RST pin.
1: Source of last reset was /RST pin.
FERROR
Bit6
R
C0RSEF
Figure 10.4. RSTSRC: Reset Source Register
R/W
Bit5
SWRSF
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.1
Bit3
R
R/W
Bit2
PORSF
R/W
Bit1
PINRSF
Bit0
R
SFR Address:
Reset Value
Variable
0xEF