C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 178

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
16.3.2. Clock Low Extension
2
SMBus provides a clock synchronization mechanism, similar to I
C, which allows devices with different speed capa-
bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to
communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period,
effectively decreasing the serial clock frequency.
16.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas-
ter cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies
that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condi-
tion. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detect-
ing the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload
when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after
25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the
SMBus in the event of an SCL low timeout.
16.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is desig-
nated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high
for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a Master START, the START will
be generated following this timeout. Note that a clock source is required for free timeout detection, even in a slave-
only implementation.
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