C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 151

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as
shown in Figure 15.8. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half
IN, half OUT).
15.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint,
and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode,
the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are
used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to form a sin-
gle IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The end-
point direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see
Figure 15.23).
15.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is
halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint
is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When
0x07FF
0x07C0
0x07BF
0x03FF
0x073F
0x063F
0x043F
0x0740
0x0640
0x0440
0x0400
0x0000
(1024 bytes)
User XRAM
(128 bytes)
(256 bytes)
(512 bytes)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Figure 15.8. USB FIFO Allocation
Free
Rev. 1.1
USB Clock Domain
System Clock Domain
IN, OUT, or both (Split
Configurable as
Mode)
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