C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 81

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C8051F320

Manufacturer Part Number
C8051F320
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet

Specifications of C8051F320

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs
found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the
sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to
0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as
byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for
future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding
pages of the datasheet, as indicated in Table 9.3, for a detailed description of each register.
E8
E0
D8
D0
C8 TMR2CN
C0
B8
B0
A8
A0
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
ADC0LTH
F8
F0
98
90
88
80
(bit addressable)
ADC0CN
SMB0CN
PCA0CN
SPI0CN
SCON0
TCON
ACC
PSW
0(8)
P3
P2
P1
P0
IP
IE
B
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3
CLKMUL
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
OSCXCN
TMR3CN
REG0CN
SPI0CFG
SMB0CF
CLKSEL
Address
P0MDIN
REF0CN
PCA0L
SBUF0
TMOD
0xBC
0xBD
XBR0
0xC4
0xC3
0xBE
0xC6
Table 9.2. Special Function Register (SFR) Memory Map
0xE0
0xE8
1(9)
SP
TMR2RLL TMR2RLH
SMB0DAT ADC0GTL ADC0GTH
TMR3RLL TMR3RLH
SPI0CKR
P1MDIN
OSCICN
EMI0CN
CPT1CN
AMX0N
Description
Accumulator
ADC0 Configuration
ADC0 Control
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
ADC0 Low
ADC0 Less-Than Compare Word High
PCA0H
Table 9.3. Special Function Registers
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4
SPI0DAT
P2MDIN
CPT0CN
OSCICL
AMX0P
DPH
3(B)
TL1
Rev. 1.1
P0MDOUT P1MDOUT P2MDOUT
ADC0CF
CPT1MD
P3MDIN
P0SKIP
TMR2L
TMR3L
IT01CF
TH0
4(C)
ADC0LTL
CPT0MD
TMR2H
TMR3H
P1SKIP
ADC0L
TH1
5(D)
ADC0LTH
USB0ADR
C8051F320/1
CPT1MX
CKCON
ADC0H
P2SKIP
FLSCL
EIP1
EIE1
6(E)
P3MDOUT
USB0XCN
USB0DAT
VDM0CN
CPT0MX
RSTSRC
FLKEY
PSCTL
PCON
EIE2
EIP2
7(F)
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