AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 94
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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10.1.2
94
AT90CAN32/64/128
Synchronous External Interrupt Control Register B – EICRB
Table 10-1.
Note:
Table 10-2.
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: Synchronous External Interrupt 7 - 4 Sense
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Table 10-3.
Note:
Bit
Read/Write
Initial Value
ISCn1
Symbol
ISCn1
Control Bits
t
0
0
1
1
0
0
1
1
INT
1. n = 3, 2, 1 or 0.
1. n = 7, 6, 5 or 4.
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
ISCn0
Parameter
Minimum pulse width for asynchronous
external interrupt
0
1
0
1
0
1
0
1
ISC71
Asynchronous External Interrupt Characteristics
R/W
Asynchronous External Interrupt Sense Control
Synchronous External Interrupt Sense Control
7
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt request.
The rising edge between two samples of INTn generates an interrupt request.
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
ISC70
R/W
6
0
ISC61
R/W
5
0
Table
ISC60
R/W
4
0
10-3. The value on the INT7:4 pins are sampled
ISC51
R/W
3
0
Condition
ISC50
R/W
2
0
(1)
(1)
ISC41
R/W
1
0
Min
ISC40
R/W
0
0
Typ
50
EICRB
Max
7679H–CAN–08/08
Units
ns
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