AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 302
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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23.3.2.4
23.3.3
23.3.4
23.4
302
Boundary-scan Specific JTAG Instructions
AT90CAN32/64/128
Reset Register
Boundary-scan Chain
Device ID
The full Device ID is listed in
Table 23-4.
The Reset Register is a test data register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Register can also replace the function of the unimplemented optional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse set-
tings for the clock options, the part will remain reset for a reset time-out period (refer to
Clock” on page
latched, so the reset will take place immediately, as shown in
Figure 23-2. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not
implemented, but all outputs with tri-state capability can be set in high-impedant state by using
the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
Version
AT90CAN32 revision A
AT90CAN64 revision A
AT90CAN128 revision A
“Boundary-scan Chain” on page 304
Device ID
37) after releasing the Reset Register. The output from this data register is not
From Other Internal and
External Reset Sources
Table 23-4
From TDI
ClockDR • AVR_RESET
following the AT90CAN32/64/128 version.
for a complete description.
D
Q
JTAG Device ID (Hex)
Figure
0x0958103F
0x0968103F
0x0978103F
23-2.
Internal reset
To TDO
7679H–CAN–08/08
“System
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