AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 78
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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9.3.4
78
AT90CAN32/64/128
Alternate Functions of Port C
Table 9-8.
The Port C has an alternate function as the address high byte for the External Memory Interface.
The Port C pins with alternate functions are shown in
Table 9-9.
The alternate pin configuration is as follows:
• A15/CLKO – Port C, Bit 7
A15, External memory interface address 15.
CLKO, Divided System Clock: The divided system clock can be output on the PC7 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTC7 and DDC7 settings. It will also be output during reset.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Port Pin
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Overriding Signals for Alternate Functions in PB3..PB0
Port C Pins Alternate Functions
PB3/MISO
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPI SLAVE
OUTPUT
0
0
0
SPI MASTER
INPUT
–
SPE • MSTR
Alternate Function
A15/CLKO (External memory interface address 15 or Divided System
Clock)
A14 (External memory interface address 14)
A13 (External memory interface address 13)
A12 (External memory interface address 12)
A11 (External memory interface address 11)
A10 (External memory interface address 10)
A9 (External memory interface address 9)
A8 (External memory interface address 8)
PB2/MOSI
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MASTER
OUTPUT
0
0
0
SPI SLAVE
INPUT • RESET
–
Table
PB1/SCK
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
0
0
0
SCK INPUT
–
9-9.
PB0/SS
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
0
0
0
SPI SS
–
7679H–CAN–08/08
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