AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 178
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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AT90CAN32/64/128
Figure 17-1. USARTn Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USARTn (listed
from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all
units. The Clock Generation logic consists of synchronization logic for external clock input used
by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USARTn module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
1. Refer to
on page 79
Figure 1-2 on page 5
for USARTn pin placement.
UCSRAn
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn (Transmit)
UBRRn[H:L]
or
(1)
Figure 1-3 on page
UCSRBn
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
6,
CHECKER
PARITY
CLOCK
PARITY
DATA
Table 9-15 on page
CLKio
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
RX
83, and
PIN
TX
Receiver
UCSRCn
7679H–CAN–08/08
Table 9-10
XCKn
RxDn
TxDn
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