AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 214
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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18.6.4
18.6.5
214
AT90CAN32/64/128
TWI Data Register – TWDR
TWI (Slave) Address Register – TWAR
• Bits 1.0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 18-2.
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register
cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-
ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted
in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep
mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost
bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is
controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7.0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the TWI Serial Bus.
• Bits 7.1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit. The TWAR should be loaded with
the 7-bit slave address to which the TWI will respond when programmed as a slave transmitter
or receiver, and not needed in the master modes. In multimaster systems, TWAR must be set in
masters which can be addressed as slaves by other masters.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TWPS1
0
0
1
1
TWD7
TWA6
TWI Bit Rate Prescaler
R/W
R/W
7
1
7
1
TWD6
TWA5
R/W
R/W
6
1
6
1
“Bit Rate Generator Unit” on page
TWD5
TWA4
R/W
R/W
5
1
5
1
TWPS0
0
1
0
1
TWD4
TWA3
R/W
R/W
4
1
4
1
TWD3
TWA2
R/W
R/W
3
1
3
1
Prescaler Value
1
4
16
64
TWD2
TWA1
R/W
R/W
2
1
2
1
210. The value of TWPS1.0 is used
TWD1
TWA0
R/W
R/W
1
1
1
1
TWGCE
TWD0
R/W
R/W
0
1
0
0
TWDR
TWAR
7679H–CAN–08/08
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