AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 147
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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14.2.1
14.3
14.4
7679H–CAN–08/08
Timer/Counter Clock Sources
Counter Unit
Definitions
The following definitions are used extensively throughout the section:
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source is selected by the clock select logic which is controlled by the
clock select (CS22:0) bits located in the Timer/Counter control register (TCCR2).The clock
source clk
is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to
TOSC1 and TOSC2 or directly from TOSC1. For details on asynchronous operation, see
chronous Status Register – ASSR” on page
“Timer/Counter2 Prescaler” on page
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
14-2
Figure 14-2. Counter Unit Block Diagram
Figure 14-3.
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surrounding environment.
count
direction
clear
clk
top
bottom
T2
T2
is by default equal to the MCU clock, clk
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is depen-
dent on the mode of operation.
DATA BUS
TCNTn
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock.
Signalizes that TCNT2 has reached maximum value.
Signalizes that TCNT2 has reached minimum value (zero).
direction
163.
count
clear
bottom
Control Logic
160. For details on clock sources and prescaler, see
top
TOVn
(Int.Req.)
I/O
clk
Tn
. When the AS2 bit in the ASSR Register
Prescaler
AT90CAN32/64/128
clk
TnS
Oscillator
T/C
clk
I/O
“Asyn-
Figure
TOSC2
TOSC1
147
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