AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 224
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 18-4.
18.8.3
224
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x38
0x40
0x48
0x50
0x58
AT90CAN32/64/128
Slave Receiver Mode
Status of the Two-wire Serial Bus
and Two-wire Serial Interface
Hardware
A START condition has been
transmitted
A repeated START condition has
been transmitted
Arbitration lost in SLA+R or NOT
ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
Status Codes for Master Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see
Figure
zero or are masked to zero.
Figure 18-15. Data Transfer in Slave Receiver Mode
18-15). All the status codes mentioned in this section assume that the prescaler bits are
SDA
SCL
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
Device 1
RECEIVER
Application Software Response
SLAVE
To TWCR
STA
X
X
X
0
1
0
0
1
0
1
0
0
1
0
1
0
TRANSMITTER
Device 2
STO
MASTER
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
TWEA
Device 3
X
X
X
X
X
0
1
X
X
X
1
X
X
X
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to master transmitter mode
Two-wire Serial Bus will be released and not addressed
slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
........
Device n
R1
7679H–CAN–08/08
V
CC
R2
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