ATTINY26-16PI Atmel, ATTINY26-16PI Datasheet - Page 55

• Manufacturer Part Number: ATTINY26-16PI
• Description: IC AVR MCU 2K 16MHZ IND 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26-16PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 28. Overriding Signals for Alternate Functions in PB3..PB0
Notes:
1477K–AVR–08/10
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. Enabling of the Timer/Counter1 Compare match outputs and Timer/Counter1 PWM Outputs OC1A/OC1B and OC1A/OC1B
2. Note that the PCINT0 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE0 flag in GIMSK is set
3. The Two-wire and Three-wire USI-modes are described in “Universal Serial Interface – USI” on page 80.
4. Shift clock (SCL) hold for USI is in described “Universal Serial Interface – USI” on page 80.
5. USI start up interrupt is enabled if both the Global Interrupt Flag is enabled and the USISIE flag in the USICR Register is set
6. Data Output (DO) is valid in USI Three-wire mode and the operation is described in “Universal Serial Interface – USI” on
7. Operation of the data pin SDA in USI Two-wire mode and DI in USI Three-wire mode in “Universal Serial Interface – USI” on
8. Not operator is marked with “~”.
are described in the section “8-bit Timer/Counter1” on page 67.
and the alternate function of the pin is disabled as described in “Pin Change Interrupt” on page 62.
as described in “Universal Serial Interface – USI” on page 80.
page 80.
page 80.
PB3/OC1B/PCINT0
0
0
0
0
OC1B_ENABLE
OC1B
PCINT0_ENABLE
~OC1B_ENABLE
1
PCINT0
–
(1)
(1)
(2)
•
PB2/SCK/SCL/OC1B/PCI
NT0
0
USI_TWO-WIRE
(USI_SCL_HOLD
~
USI_TWO-WIRE
DDB2 | OC1B_ENABLE
~(USI_TWO-WIRE •
DDB2) • OC1B
~(USI_TWO-WIRE |
USI_THREE-WIRE |
OC1B_ENABLE) •
PCINT0_ENABLE
USI_START_I.ENABLE
1
PCINT0, SCL, SCK
–
USI_TWO-WIRE
(8)
PORTB2) • DDB2
(3)
(3)
(3)
(4)
(2)
•
|
|
(5)
(1)
PB1/DO/OC1A/PCINT0
0
0
0
0
USI_THREE-WIRE
OC1A_ENABLE
USI_THREE-WIRE
DO
WIRE • OC1A_ENABLE
• OC1A
~(USI_THREE-WIRE |
OC1A_ENABLE) •
PCINT0_ENABLE
1
PCINT0
–
(6)
| ~USI_THREE-
(1)
(2)
(3)
(3)
|
•
(1)
PB0/DI/SDA/OC1A
0
USI_TWO-WIRE
(~SDA | ~PORTB0) •
DDB0
USI_TWO-WIRE
|
OC1A_ENABLE
~(USI_TWO-WIRE•
DDB0) •
OC1A_ENABLE
~(USI_TWO-WIRE
USI_THREE-WIRE
OC1A_ENABLE
PCINT0_ENABLE
USI_START_I.ENABLE
1
PCINT0, SDA
–
USI_TWO-WIRE
(1)
(1)
(1)
(3)
(3)
(3)
(2)
) •
• DDB0
• OC1A
(3)
(3)
|
|
|
(5)
55