ATTINY26-16PI Atmel, ATTINY26-16PI Datasheet - Page 16

• Manufacturer Part Number: ATTINY26-16PI
• Description: IC AVR MCU 2K 16MHZ IND 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26-16PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Memories
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crys-
tal for the chip. No internal clock division is used.
Figure 16 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 16. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 17 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 17. Single Cycle ALU Operation
T1
T2
T3
T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described in Figure
18.
ATtiny26(L)
16
1477K–AVR–08/10