UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 639

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Data Retention Characteristics
STOP Mode (T
Data retention voltage
Data retention current
Supply voltage rise time
Supply voltage fall time
Supply voltage retention time
(for STOP mode setting)
STOP mode release signal input
time
Data retention input voltage, high
Data retention input voltage, low
Note When reset mode (LVIM.LVIMD bit = 0) of low-voltage detector (LVI) is not used:
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated
STOP mode release interrupt (INTP0, etc.)
STOP mode release interrupt (INTP0, etc.)
V
DD
POC detection voltage (V
When reset mode (LVIM.LVIMD bit = 1) of low-voltage detector (LVI) is used:
LVI detection voltage (V
/EV
Parameter
operating range.
• When LVI (reset mode) is not used: POC detection voltage (V
• When LVI (reset mode) is used: LVI detection voltage (V
If the voltage level reaches the POC detection voltage (V
or to LVI detection voltage (V
automatically released because internal reset (POCRES/LVIRES) is effected.
DD
A
(operating voltage lower limit)
= −40 to +85°C, V
(released by falling edge)
(released by rising edge)
RESET (input)
LVI0
Symbol
SS
V
I
V
V
t
POC0
DDDR
t
t
t
DREL
DDDR
HVD
CHAPTER 19 ELECTRICAL SPECIFICATIONS
RVD
FVD
IHDR
ILDR
/V
3.5 V
= EV
LVI1
)
STOP mode setting
)
SS
In STOP mode
After reset other
than power supply
V
V
V
All input pins
All input pins
DD
DD
DD
= AV
User’s Manual U17716EJ2V0UD
= V
LVI0
SS0
DDDR
/V
= AV
LVI1
t
HVD
Conditions
) when LVI (reset mode) is used, the STOP mode is
SS1
= 0 V)
V
V
DD
DD
t
FVD
, EV
, EV
DD
DD
LVI0
V
V
V
V
POC0
DDDR
IHDR
IHDR
ILDR
/V
0.9V
) when LVI (reset mode) is not used
LVI1
Note
MIN.
POC0
1.9
1
1
0
0
0
DDDR
) or higher
) or higher
t
RVD
TYP.
30
STOP mode release
t
DREL
signal input
0.1V
MAX.
V
Note
200
5.5
DDDR
DDDR
Unit
ms
ms
μ
μ
μ
V
V
V
V
A
s
s
637