UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 152

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

150
(6) TMPn option register 0 (TPnOPT0)
Note Valid only for TMP0 and TMP2. Be sure to clear bits 5 and 4 of TMP1 and TMP3 to 0.
Cautions 1. Rewrite the TPkCCS1 and TPkCCS0 bits when the TPkCE bit = 0. (The same value can be
The TPnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. Be sure to clear bits 1 to 3, 6, and 7 to “0”.
(n = 0 to 3,
TPnOPT0
k = 0, 2)
written when the TPkCE bit = 1.) If rewriting was mistakenly performed, clear the TPkCE bit
to 0 and then set the bits again.
After reset: 00H
TPkCCS1
TPkCCS0
Set (1)
Reset (0)
The TPkCCS1 bit setting is valid only in the free-running timer mode.
The TPkCCS0 bit setting is valid only in the free-running timer mode.
• The TPnOVF bit is set to 1 when the 16-bit counter value overflows from FFFFH
• An overflow interrupt request signal (INTTPnOV) is generated at the same time
• The TPnOVF bit is not cleared to 0 even when the TPnOVF bit or the TPnOPT0
• Before clearing the TPnOVF bit to 0 after generation of the INTTPnOV signal, be
• The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set
to 0000H in the free-running timer mode or the pulse width measurement mode.
that the TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes
other than the free-running timer mode and the pulse width measurement mode.
register is read when the TPnOVF bit = 1.
sure to confirm (by reading) that the TPnOVF bit is set to 1.
to 1 by software. Writing 1 has no effect on the operation of TMPn.
0
1
0
1
0
7
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnOVF
Note
Note
Compare register selected
Capture register selected (cleared by TPkCTL0.TPkCE bit = 0)
Compare register selected
Capture register selected (cleared by TPkCTL0.TPkCE bit = 0)
R/W
6
0
Address:
User’s Manual U17716EJ2V0UD
TPkCCS1
Overflow occurred
0 written to TPnOVF bit or TPnCTL0.TPnCE bit = 0
TPkCCR1 register capture/compare selection
TPkCCR0 register capture/compare selection
5
Note
TPkCCS0
TMPn overflow detection flag
TP0OPT0 FFFFF645H, TP1OPT0 FFFFF665H,
TP2OPT0 FFFFF685H, TP3OPT0 FFFFF6A5H
4
Note
3
0
2
0
1
0
TPnOVF
<0>