UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 506

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

504
CB0TMS
Notes 1. These bits can only be rewritten when the CB0PWR bit = 0.
CB0DIR
•
CB0SCE
• In master mode
• In slave mode
• In single transmission or transmission/reception mode, or continuous transmission
When using single transmission or transmission/reception mode with communication
type 2 or 4 (CB0CTL1.CB0DAP bit = 1), write the transfer data to the CB0TX
register after checking that the CB0STR.CB0TSF bit is 0.
This bit enables or disables the communication start trigger.
(a) In single reception mode
(b) In continuous reception mode
This bit enables or disables the communication start trigger.
(a) In single reception mode or continuous reception mode
or transmission/reception mode
The function of the CB0SCE bit is invalid. It is recommended to set this bit to 1.
0
1
0
1
0
1
Clear the CB0SCE bit to 0 before reading the receive data (CB0RX register)
Clear the CB0SCE bit to 0 one communication clock before reception of the
last data is ended
Set the CB0SCE bit to 1
Note 1
Note 1
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
2. If the CB0SCE bit is read while it is 1, the next communication
3. The CB0SCE bit is not cleared to 0 one communication clock
4. To start the reception, a dummy read is necessary.
Single transfer mode
Continuous transfer mode
Communication start trigger invalid
Communication start trigger valid
MSB first
LSB first
However, the CB0PWR can be set to 1 at the same time as these
bits are rewritten.
operation is started.
before the end of the last data reception, the next communication
operation is automatically started.
To start communication operation again after reading the last
data, set the CB0SCE bit to 1 and perform a dummy read of the
CB0RX register.
Specification of transfer direction mode (MSB/LSB)
Note 3
Specification of start transfer disable/enable
User’s Manual U17716EJ2V0UD
.
Note 4
Transfer mode specification
.
Note 2
.
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